Stacked Transistor Contact Formation Using a Dummy Contact Layer
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Solution Overview
Problem
The challenge in forming stacked transistor devices lies in the process flow, particularly in forming source and drain contacts for both bottom and top devices, which introduces inefficiencies and potential interface degradation due to elevated temperatures during epitaxy and replacement metal gate processes.
Innovation Solution
A method involving the formation of parallel fin structures with sacrificial gates, epitaxial source/drain bodies, a dummy contact layer, and a replacement metal gate process, where the dummy layer provides masking and is replaced with contact metals to form discrete source/drain contacts, mitigating interface degradation and facilitating efficient contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a monolithic process is used to form stacked transistor devices with simultaneous gate patterning, then device integration density is improved, but source and drain contact formation becomes complex and prone to interface degradation
Solution Approach 1:
The patent segments the contact formation process into distinct stages: first forming bottom source/drain contacts, then forming top source/drain contacts. This is achieved by selectively removing sacrificial layers and forming contacts in a staged manner rather than simultaneously, thereby simplifying the overall process while maintaining vertical integration.
Solution Approach 2:
The patent performs preliminary actions by forming bottom source/drain contacts and their isolation structures before forming top source/drain contacts. This sequential approach allows each contact formation to be optimized independently, reducing process complexity and interface degradation risks.
2Manufacturing precision
If elevated temperature processes are used for epitaxy and replacement metal gate, then material quality is improved, but source/drain contact interface degradation occurs
Solution Approach 1:
The patent divides the high-temperature processing into separate stages for bottom and top contacts. By forming bottom contacts, performing isolation, then forming top contacts with their own isolation, each interface is protected from prolonged thermal exposure, maintaining material quality while preventing interface degradation.
Solution Approach 2:
The patent introduces isolation dielectric layers as intermediary structures between source/drain contacts and channel regions. These intermediary layers act as protective barriers during high-temperature replacement metal gate processes, preventing direct thermal damage to contact interfaces while allowing the necessary heat treatment for material quality.
3Productivity
If source and drain contacts are formed for both bottom and top devices simultaneously, then process efficiency is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent segments contact formation into sequential bottom and top contact processes rather than simultaneous formation. This staged approach, while taking more steps, allows each contact to be precisely formed and isolated independently, achieving better manufacturing precision that would be difficult to obtain through simultaneous formation.
Solution Approach 2:
The patent performs preliminary contact formation and isolation for bottom devices before addressing top devices. This preliminary action ensures precise alignment and interface quality for bottom contacts, and the established structure serves as a foundation for subsequent top contact formation with equivalent precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables reliable and efficient formation of source/drain contacts for stacked transistor devices, reducing the risk of interface degradation and improving the process flow by providing a large access area for the replacement metal contact process, suitable for monolithic CFET devices and other stacked transistor configurations.
Implementation Method 1
forming bottom source/drain bodies for each bottom transistor device by epitaxy; forming top source/drain bodies for each top transistor device over the bottom dummy contact layer by epitaxy
Implementation Method 2
removing a top portion of the dummy material by an etch back process such that a bottom portion of the dummy material remains to cover the bottom source/drain bodies
Data Source
AI summary
In one aspect, a method of forming a semiconductor device including a plurality of stacked transistor devices having a bottom transistor device and a top transistor device can include: forming a plurality of parallel fin structures on a substrate; forming a sacrificial gate across the fin structures; forming bottom source/drain bodies for each bottom transistor device by epitaxy; forming a bottom dummy contact layer covering the bottom source/drain bodies; forming top source/drain bodies for each top transistor device over the bottom dummy contact layer by epitaxy; depositing an insulating material over the bottom dummy contact layer and the top source/drain bodies; replacing the sacrificial gate with a functional gate stack by a replacement metal gate process; patterning holes extending through the insulating material, with each hole exposing an upper surface portion of the bottom dummy contact layer; replacing the bottom dummy contact layer with one or more contact metals, which can include etching the dummy material via the holes and thereafter depositing the one or more contact metals via the holes; and etching cuts through the contact metal via the holes.