Stacked Transistor Structure With Elevated Source-Drain Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor device manufacturing methods face limitations in miniaturization, leading to increased contact resistance and leakage current due to thin semiconductor layers, which hinder high integration and performance.
Innovation Solution
A semiconductor device with elevated source and drain regions above the channel region, combined with a method of forming a semiconductor device that includes a first interlayer insulation layer, a second semiconductor layer with source, drain, and channel regions, and a gate pattern, where the elevated layer increases the contact area with conducting columns, reducing contact resistance and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the semiconductor layer is thinly formed to reduce leakage current, then leakage current is reduced, but contact area decreases and contact resistance increases
Solution Approach 1:
The patent introduces an elevated layer that protrudes vertically from the semiconductor layer surface, transforming a two-dimensional contact interface into a three-dimensional structure. This vertical extension increases the contact area between the conducting column and semiconductor material without increasing the lateral footprint, thereby reducing contact resistance while maintaining thin channel thickness for low leakage current.
Solution Approach 2:
The elevated layer is formed within the existing semiconductor structure, nested between the channel region and the conducting column. This nested configuration allows the elevated layer to serve as an intermediate structure that enhances contact area without adding external components, resolving the contradiction between thin layer requirements and contact resistance.
2Productivity
If electronic elements are miniaturized to achieve high integration, then integration density increases, but manufacturing limitations prevent further miniaturization
Solution Approach 1:
The patent utilizes the vertical dimension by forming an elevated layer that protrudes from the semiconductor layer surface. This three-dimensional structure allows for increased functional density without requiring further lateral miniaturization of the transistor components, thereby overcoming manufacturing limitations while achieving higher integration density.
Solution Approach 2:
The semiconductor structure is segmented into distinct functional regions: the channel region, the elevated layer, and the conducting column. This segmentation allows each component to be optimized independently - the channel can be miniaturized for high density while the elevated layer provides enhanced contact area, resolving the contradiction between integration density and manufacturability.
3Reliability
If the contact area between conducting column and source/drain regions is increased, then contact resistance decreases, but device area increases
Solution Approach 1:
The elevated layer extends vertically from the semiconductor layer surface, increasing the contact area between the conducting column and semiconductor material in the vertical dimension. This three-dimensional contact structure reduces contact resistance without requiring additional lateral space, thereby maintaining compact device footprint while improving electrical contact.
Data Source
AI summary
A semiconductor device includes a first semiconductor layer, a first interlayer insulation layer, a second semiconductor layer, and a gate pattern. The first interlayer insulation layer covers the first semiconductor layer. The second semiconductor layer is formed on the first interlayer insulation layer and includes source regions, drain regions, and a channel region interposed between the source region and the drain region. The gate pattern includes a gate insulation layer on the channel region of the second semiconductor layer. At least one of the source regions and the drain regions includes an elevated layer having a top surface higher than that of the channel region.