Cross-Coupled Stacked Transistor Layout for FEOL Gate Routing
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Solution Overview
Problem
Current semiconductor technologies face challenges in scaling beyond 5 nm due to increasing process complexities and costs, particularly in forming efficient connections between stacked transistors in integrated circuit chips.
Innovation Solution
The semiconductor structure employs a cross-coupled stacked transistor configuration where conductive structures connect bottom and top gate conductors of adjacent transistors, enabling electrical connections in unused front-end-of-line space, reducing the need for additional connections in the back-end-of-line and optimizing transistor array layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional chip scaling is continued, then transistor density increases, but process complexities and costs escalate
Solution Approach 1:
The patent transitions from planar transistor arrangements to three-dimensional stacked transistor structures. Multiple transistors are stacked vertically to form towers, utilizing the vertical dimension to increase transistor density without proportionally increasing process complexity. This dimensional change allows continued scaling while managing fabrication challenges.
Solution Approach 2:
The patent segments the transistor array into modular stacked units or towers. Each stack contains multiple transistors arranged vertically, and these stacks can be independently formed and connected. This segmentation allows for systematic fabrication and reduces overall process complexity by breaking down the complex task of creating high-density transistor arrays into manageable modular units.
2Adaptability or versatility
If more connections are made in back-end-of-line, then transistor interconnectivity increases, but manufacturing complexity and cost increase
Solution Approach 1:
The patent performs preliminary actions by forming conductive structures and establishing electrical connections between stacked transistors during the front-end-of-line fabrication process. Cross-coupling connections are created as part of the initial transistor stack formation rather than adding them later in the back-end-of-line. This preliminary establishment of connections reduces the number of subsequent manufacturing steps required.
Solution Approach 2:
The patent merges the formation of transistor stacks with the creation of cross-coupling connections. The same fabrication processes used to create the stacked transistor structures also establish the electrical interconnections between them. By combining these functions into a single integrated structure, the patent reduces manufacturing complexity and eliminates the need for separate connection-making steps in the back-end-of-line.
3Area of stationary object
If wafer real estate is minimized, then chip area decreases, but available space for connections is reduced
Solution Approach 1:
The patent resolves this contradiction by moving connections into the vertical dimension through stacked transistor towers. Multiple transistors are connected in the vertical direction rather than requiring lateral routing, which would consume valuable horizontal wafer real estate. This vertical stacking enables efficient use of chip area while maintaining necessary connection pathways.
Solution Approach 2:
The patent implements nesting by placing conductive structures and connection pathways within and between the stacked transistor towers. The cross-coupling connections are integrated into the vertical stack structure itself, with conductive elements nested between or within adjacent stacks. This nesting approach maximizes the use of available three-dimensional space, enabling connections without requiring additional horizontal area.
Data Source
AI summary
A semiconductor structure including a first stacked transistor structure adjacent to a second stacked transistor structure, and a first conductive structure in direct contact with and electrically connecting a bottom gate conductor of the first stacked transistor structure and a top gate conductor of the second stacked transistor structure.