Stacked Transistor Gate Structure for Independent Lower-Gate Contact
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Solution Overview
Problem
Existing integrated circuit (IC) fabrication methods face challenges in providing independent gate contact connections for stacked transistors, leading to interference between upper and lower gates of adjacent transistors, which affects independent gate control.
Innovation Solution
A semiconductor structure is developed with a gate extension into a shallow trench isolation region, featuring non-conductive frontside and backside gate cuts that isolate upper and lower transistors, allowing for independent gate contact through a contact coupled to the lower transistor gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate structure is used for stacked transistors, then the structure is simple and manufacturing is easier, but independent gate control between upper and lower transistors cannot be achieved due to interference
Solution Approach 1:
The gate structure is segmented into separate upper gate and lower gate regions through non-conductive frontside and backside gate cuts. These cuts divide the continuous gate structure into isolated segments, allowing independent electrical control of each transistor stack while maintaining physical separation. The gate extension into the shallow trench isolation region further segments the gate structure laterally, preventing interference between adjacent transistor stacks.
Solution Approach 2:
Non-conductive gate cuts act as intermediary elements that electrically isolate different gate regions. These non-conductive sections serve as mediators that prevent direct electrical connection between upper and lower gates, enabling independent control while maintaining structural continuity. The shallow trench isolation region also serves as an intermediary barrier that electrically isolates adjacent transistor stacks.
2Reliability
If gate structures of adjacent stacked transistors are isolated, then independent gate control is achieved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The fabrication process is segmented into distinct frontside and backside gate cut operations, allowing isolation to be achieved through sequential processing steps. The gate extension into the shallow trench isolation region provides additional lateral segmentation that simplifies the overall isolation process by creating natural boundaries between adjacent transistor stacks.
Solution Approach 2:
The gate structure is extended into the shallow trench isolation region, adding a lateral dimension to the gate structure. This dimensional extension creates natural isolation boundaries that simplify the fabrication process by reducing the need for complex etching and deposition steps to achieve electrical isolation between adjacent stacks.
3Object-affected harmful factors
If a gate extension into shallow trench isolation region is implemented, then interference between adjacent transistors is reduced, but device structure complexity increases
Solution Approach 1:
The gate structure is extracted or extended into the shallow trench isolation region, which acts as a pre-defined isolation zone. By placing the gate extension into this dedicated isolation region, electrical interference between adjacent transistors is naturally reduced without requiring additional complex isolation structures or materials.
Solution Approach 2:
The shallow trench isolation region serves multiple functions: it provides electrical isolation between adjacent transistor stacks, accommodates the gate extension, and maintains structural support. This multi-functional use of the isolation region reduces overall device complexity by eliminating the need for separate isolation structures.
Data Source
AI summary
Embodiments of the invention include a semiconductor structure having first stacked transistors including a first upper transistor over a first lower transistor. Second stacked transistors are adjacent to the first stacked transistors. A gate structure includes a gate extension into a shallow trench isolation region, where a non-conductive frontside gate cut through the gate structure isolates the first stacked transistors and the second stacked transistors, where a contact through the non-conductive frontside gate cut contacts the gate extension and is coupled to the first lower transistor.