Stacked Transistor Contact Structure for Lower Gate Coupling
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Solution Overview
Problem
As semiconductor devices progress towards increased device density and lower costs, challenges arise from fabrication and design, particularly in stacked device configurations like CFETs, where capacitance between vertical interconnects and adjacent gate structures, as well as source/drain contacts, hinder performance.
Innovation Solution
The formation of semiconductor devices with vertically stacked transistors includes gate structures wrapping around semiconductor nanostructures and source/drain regions, with dielectric features and source/drain contacts extending through these structures to reduce capacitance, utilizing selective etching and epitaxial growth to create isolated and connected regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertically stacked transistors are implemented to increase device density, then integration density is improved, but capacitance between vertical interconnects and adjacent gate structures increases
Solution Approach 1:
The patent segments the vertical interconnect structure by introducing dielectric material between the vertical interconnect and adjacent gate structures. This segmentation creates electrical isolation that reduces unwanted capacitance while maintaining the vertical stacking configuration for high density.
Solution Approach 2:
The patent introduces dielectric material as an intermediary between the vertical interconnect and adjacent gate structures. This intermediary layer reduces direct electrical coupling and capacitance effects while allowing the compact vertical transistor stacking to be maintained.
2Reliability
If gate structures wrap around semiconductor nanostructures to improve control, then transistor performance is improved, but fabrication complexity increases
Solution Approach 1:
The patent implements gate structures that wrap around semiconductor nanostructures in a nested configuration, with the gate electrode surrounding the channel-forming nanostructure. This nested arrangement improves gate control over the channel while the self-aligned fabrication process manages the complexity.
Solution Approach 2:
The patent uses preliminary patterning and self-aligned fabrication processes where earlier fabrication steps automatically position subsequent structures. This preliminary action reduces the need for complex alignment steps in later fabrication, managing overall fabrication complexity despite the wrapped gate structure.
3Reliability
If source/drain contacts extend through dielectric features to reduce capacitance, then electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms openings through dielectric features at predetermined locations during earlier fabrication steps, before final contact deposition. This preliminary action establishes precise alignment paths that guide subsequent contact material deposition, reducing the precision burden on later steps.
Solution Approach 2:
The source/drain contacts are nested within openings formed through dielectric features, creating a hierarchical structure where the contact is positioned within a pre-formed pathway. This nested arrangement ensures proper alignment and electrical connectivity while managing manufacturing precision requirements through self-alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the performance of semiconductor devices by reducing capacitance between vertical interconnects and adjacent gate structures, enhancing electrical connectivity and efficiency.
Implementation Method 1
capacitance between the vertical interconnects and adjacent gate structures, as well as capacitance between the source/drain contacts and adjacent gate structures
Implementation Method 2
utilizing selective etching and epitaxial growth to create isolated and connected regions
Data Source
AI summary
A semiconductor device and the method of forming the same are provided. The semiconductor device may include an isolation region, a first dielectric layer over the isolation region, a second dielectric layer over the first dielectric layer, a first source/drain region in the second dielectric layer, a first nanostructure on a sidewall of the first source/drain region, a first gate electrode around the first nanostructure, a first source/drain contact over the first source/drain region electrically connected to the first source/drain region, a conductive feature in the first dielectric layer and the isolation region, and a dielectric feature over the conductive feature and in the second dielectric layer. A first portion of the first source/drain contact may be between two inner sidewalls of the dielectric feature, and the first portion of the first source/drain contact may be electrically connected to the conductive feature.