Stacked Transistor Gate Dielectrics for Threshold Voltage Control
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Solution Overview
Problem
The challenge in setting the threshold voltage of gate-all-around transistors, particularly in stacked configurations with nanoribbons or nanosheets, is due to the limited thickness of high-κ dielectric and work function metal layers caused by the small spacing between semiconductor bodies, leading to variations in threshold voltage.
Innovation Solution
The use of different high-κ gate dielectrics and dipole species in upper and lower device portions of stacked gate-all-around transistors, with selective deposition and annealing to control the concentration of dipole species at the interface, allows for precise setting of the threshold voltage, even with near-zero thickness of the dipole species.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the thickness of high-κ dielectric and work function metal layers is reduced due to small spacing between semiconductor bodies, then device density is improved, but threshold voltage control precision deteriorates
Solution Approach 1:
The patent applies local quality by using different high-κ dielectric materials in different portions of the gate structure (first high-κ dielectric in lower device portion, second high-κ dielectric in upper device portion). This allows each region to be optimized for its specific function: the lower portion uses a dielectric with properties optimized for threshold voltage control, while the upper portion uses a dielectric optimized for other performance parameters, thereby achieving precise threshold voltage control despite reduced overall layer thickness
Solution Approach 2:
The patent employs composite materials by combining different high-κ dielectric materials (such as hafnium oxide, zirconium oxide, titanium oxide, or tantalum oxide) in a layered gate structure. This composite approach enables the gate dielectric system to simultaneously achieve high capacitance (for compact design) and precise work function control (for threshold voltage setting), resolving the contradiction between device density and threshold voltage control precision
2Manufacturing precision
If diverse gate materials are used in upper and lower device portions, then threshold voltage setting precision is improved, but device structure complexity increases
Solution Approach 1:
The patent segments the gate structure into distinct upper and lower device portions, each with its own high-κ dielectric material. This segmentation allows independent optimization of each portion's materials and properties, enabling precise threshold voltage control through the lower portion while maintaining overall structural organization. The segmented approach makes the complexity manageable by dividing it into functional modules
Solution Approach 2:
The patent achieves multi-functionality by designing the gate structure where the lower device portion's high-κ dielectric serves the primary function of threshold voltage control, while the upper device portion's high-κ dielectric provides additional functions such as electrical isolation, mechanical support, and capacitance enhancement. This multi-functional design justifies the increased material diversity by delivering multiple benefits beyond just threshold voltage setting
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and consistent setting of the threshold voltage across nanoribbon stacks, improving the reliability and performance of both n-channel and p-channel devices in CMOS circuits and other transistor configurations.
Implementation Method 1
selective deposition and annealing to control the concentration of dipole species at the interface
Implementation Method 2
annealing to control the concentration of dipole species at the interface
Data Source
AI summary
An integrated circuit includes a lower and upper device portions including bodies of semiconductor material extending horizontally between first source and drain regions in a spaced-apart vertical stack. A first gate structure is around a body in the lower device portion and includes a first gate electrode and a first gate dielectric. A second gate structure is around a body in the upper device portion and includes a second gate electrode and a second gate dielectric, where the first gate dielectric is compositionally distinct from the second gate dielectric. In some embodiments, a dipole species has a first concentration in the first gate dielectric and a different second concentration in the second gate dielectric. A method of fabrication is also disclosed.