Stacked Gate-All-Around Transistor Layout With Gate Cutting Isolation
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing the degree of integration due to the complexity of circuit patterns, particularly in stacked multi-gate transistors, which limits design flexibility and integration density.
Innovation Solution
The semiconductor device incorporates insulating patterns between gate electrodes and cutting patterns to enhance integration by electrically isolating contacts and reducing parasitic capacitance, allowing for improved design flexibility and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate transistor with three-dimensional channel is used, then current control capability and short channel effect suppression are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The gate structure is segmented into multiple independent gates (first gate electrode, second gate electrode, third gate electrode, fourth gate electrode) that can be controlled separately. This segmentation allows independent optimization of current control for different channel regions while maintaining the overall multi-gate architecture, thus improving current control capability without proportionally increasing device complexity
Solution Approach 2:
The patent transitions from planar 2D channel to three-dimensional channel structure by stacking active patterns vertically and wrapping gates around them. This dimensional change enables better electrostatic control and current management while the cutting patterns and insulating patterns help manage the complexity by creating modular sections
2Reliability
If multi-gate transistor with three-dimensional channel is used, then short channel effect suppression is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The channel is divided into multiple segments by cutting patterns that create isolated gate control regions. Each segment can be independently optimized for short channel effect suppression, and the modular approach allows systematic manufacturing processes that reduce overall complexity
Solution Approach 2:
The gate electrodes are nested around the active patterns in a wrap-around configuration, with lower and upper gates positioned at different vertical levels. This nested structure provides comprehensive electrostatic control over the three-dimensional channel, suppressing short channel effects while maintaining a compact design that manages complexity
3Adaptability or versatility
If cutting patterns are used to cut gate structure, then design flexibility and degree of integration are improved, but manufacturing precision requirements increase
Solution Approach 1:
The gate structure is divided into discrete segments by cutting patterns, allowing flexible configuration of active regions. The segmentation approach enables standardization of cutting processes and patterns, which helps manage manufacturing precision requirements while achieving high design flexibility
Solution Approach 2:
The cutting patterns are formed as preliminary structures before final gate electrode deposition. This preliminary action defines the future gate segments and active regions, allowing subsequent manufacturing steps to follow standardized procedures that reduce precision requirements while maintaining design flexibility
4Adaptability or versatility
If insulating patterns are added to electrically insulate contacts, then device functionality and integration are improved, but device complexity increases
Solution Approach 1:
The insulating patterns are merged with the cutting patterns and gate structure formation processes. By combining multiple functions into integrated structural elements, the patent achieves necessary electrical insulation and contact isolation without proportionally increasing device complexity
Solution Approach 2:
The insulating patterns serve multiple functions: electrical insulation between contacts, definition of active region boundaries, and structural support for gate electrodes. This multi-functionality reduces the need for separate dedicated insulation structures, thereby limiting the increase in device complexity while improving functionality
Data Source
AI summary
A semiconductor device includes a substrate, a lower active pattern which is spaced apart from the substrate and extends in a first direction, an upper active pattern on the lower active pattern, the upper active pattern being spaced apart from the lower active pattern and extending in the first direction, a gate structure on the substrate, the gate structure extending in a second direction intersecting the first direction, and a cutting pattern on the substrate, the cutting pattern extending in the first direction to cut the gate structure. The gate structure includes a lower gate electrode through which the lower active pattern penetrates, an upper gate electrode which is connected to the lower gate electrode and through which the upper active pattern penetrates, and an insulating pattern on one side of the cutting pattern, the insulating pattern being arranged with the upper gate electrode along the second direction.