Stacked Transistor Gate Isolation via Selective Dielectric Deposition
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Solution Overview
Problem
Integrated circuits with stacked transistor architectures face challenges in achieving effective vertical isolation between upper and lower metal gate structures due to limited space, leading to non-conformality of the isolation layer, which affects gate electrode thickness and consistency.
Innovation Solution
A conformal dielectric film is formed via selective deposition, ensuring electrical isolation between upper and lower gate structures by depositing the dielectric material only on conductive gate structures, maintaining a flat top surface and consistent thickness, even in narrow spaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional isolation layer is deposited between stacked gate structures, then electrical isolation is achieved, but the isolation layer becomes non-conformal affecting gate electrode thickness consistency
Solution Approach 1:
The method performs preliminary actions by first forming the lower gate structure, then selectively depositing the isolation layer only on the lower gate structure before forming the upper gate structure. This preliminary isolation layer deposition ensures that when the upper gate structure is formed, the isolation layer is already in place and conformal, preventing non-conformality issues and ensuring consistent gate electrode thickness.
Solution Approach 2:
The isolation layer is deposited selectively only on the lower gate structure using area-selective atomic layer deposition (ALD), creating different local properties: the isolation layer is present on the lower gate structure but absent from other regions. This localized deposition ensures conformal coverage where needed while maintaining precision in gate electrode thickness.
2Productivity
If vertical isolation is implemented in stacked transistor architecture, then transistor density is increased, but space limitations cause isolation layer non-conformality
Solution Approach 1:
The isolation layer is deposited preliminarily on the lower gate structure before the upper gate structure is formed. This preliminary action ensures that the isolation layer is conformal and properly positioned in the limited vertical space, enabling high transistor density without sacrificing isolation layer quality.
Solution Approach 2:
The lower gate structure serves a dual function: it acts as both the functional gate electrode and as the substrate for the isolation layer deposition. The lower gate structure's conductive surface naturally guides the selective deposition process, ensuring the isolation layer forms conformally without requiring additional complex processing steps.
3Area of stationary object
If dielectric material is deposited on all surfaces, then complete coverage is achieved, but gate dimension consistency is compromised due to non-conformal isolation layer
Solution Approach 1:
Area-selective ALD is used to deposit the isolation layer only on the lower gate structure surface, creating localized coverage where electrically isolated. This selective approach ensures the isolation layer is conformal to the lower gate structure while preventing excess material accumulation that would compromise upper gate dimension consistency.
Solution Approach 2:
The isolation layer is preliminarily deposited on the lower gate structure before upper gate formation. This timing ensures complete coverage of the lower gate structure surface where needed, while preventing non-conformality from affecting the upper gate structure dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables consistent gate dimensions and electrical isolation in stacked transistors, particularly for nanoribbon configurations, by reducing the impact of isolation layer non-conformality, thus enhancing transistor performance and reliability.
Implementation Method 1
The isolation layer can be formed via atomic layer deposition (ALD), for example, using area-selective ALD
Data Source
AI summary
An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and is on and conformal to a top surface of the first gate structure. In addition, a bottom surface of the second gate structure is on a top surface of the isolation structure, which is relatively flat.