Stacked Transistor Gate Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional semiconductor devices face challenges in maintaining switching speeds and reducing current leakage as device dimensions shrink, leading to increased parasitic capacitance due to gate metal between dual middle dielectric isolation layers in vertically stacked transistors.
Innovation Solution
A vertically stacked transistor design with a reduced or removed gate region between dual middle dielectric isolation (MDI) regions, utilizing inner spacers to minimize conductive material and thereby reduce parasitic capacitance, while maintaining increased device density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If gate metal is present between dual middle dielectric isolation layers in vertically stacked transistors, then device density is increased, but parasitic capacitance increases
Solution Approach 1:
The patent removes or reduces the gate metal portion between the dual middle dielectric isolation layers in vertically stacked transistors. This extraction of the harmful conductive material eliminates the parasitic capacitance pathway while preserving the essential gate functionality in the active channel regions, thereby resolving the contradiction between device density and parasitic capacitance
Solution Approach 2:
The patent applies different gate metal configurations to different regions of the vertically stacked transistor. The gate metal is maintained in regions where it provides useful function (controlling current flow through channels) but removed or reduced in regions where it creates harmful effects (between MDI layers where it contributes to parasitic capacitance). This localized differentiation resolves the contradiction by optimizing gate metal presence based on functional requirements
2Quantity of substance
If device dimensions are shrunk to follow Moore's law, then device density is increased, but switching speeds deteriorate and current leakage increases
Solution Approach 1:
The patent transitions from planar transistor geometry to vertically stacked three-dimensional transistor structures. By stacking multiple transistor layers vertically, the device achieves higher density without proportionally reducing the active channel area, thereby maintaining switching performance while increasing device density according to Moore's law
3Object-generated harmful factors
If gate structure is optimized to reduce parasitic capacitance, then device performance is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the gate structure into distinct segments: regions with full gate metal coverage over active channels and regions with reduced or removed gate metal between MDI layers. This segmentation allows the structure to achieve low parasitic capacitance in isolation regions while maintaining proper gate control in active regions, balancing performance enhancement with manufacturability
Data Source
AI summary
A transistor includes a gate structure with reduced gate region or eliminated gate region located between a top MDI region and a bottom MDI region. The reduced gate region has a reduction of conductive material therewithin and may be formed due to the presence of prefabricated wide inner spacers between the top MDI region and the bottom MDI region. The no gate region has an absence of conductive material therewithin and may be formed due to the presence of a prefabricated inner spacer that is between, and has a coplanar perimeter with, the top MDI region and the bottom MDI region. By reducing or eliminating the conductive material of the gate structure between the dual MDI structure, parasitic capacitance otherwise associated therewith is reduced.