Stacked Transistor Gate Structure Formation Using Sacrificial Protection
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Solution Overview
Problem
Integrated circuits with 3D stacked transistor configurations face challenges in forming upper and lower gate dielectric layers without damaging the thin upper gate dielectric, which can lead to unacceptable gate leakage due to processing steps affecting the thin (1 nm to 2 nm) gate dielectric layer.
Innovation Solution
A stacked transistor architecture with a common fin structure where the upper and lower transistor portions are separated by an isolation region, allowing for diverse gate structures with different compositions and geometries, including selective deposition of gate dielectric and electrode materials, and using sacrificial protective layers to protect the upper channel region during processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If processing steps are performed to form gate structures, then lower gate structure can be formed, but the thin upper gate dielectric layer is damaged leading to gate leakage
Solution Approach 1:
A sacrificial protective layer is deposited over the upper channel region to serve as an intermediary protective element during lower gate structure formation. This sacrificial layer absorbs the damage from processing steps that would otherwise harm the thin upper gate dielectric, allowing subsequent removal to reveal an intact upper gate dielectric layer.
Solution Approach 2:
The sacrificial protective layer is deposited in advance before any processing steps that could damage the upper gate dielectric. This preliminary protective measure ensures the upper gate dielectric is shielded during lower gate formation, source/drain processing, and other critical steps before being removed afterward.
2Reliability
If upper and lower gate structures are formed with different compositions and geometries, then device performance is enhanced, but processing complexity increases
Solution Approach 1:
The gate formation process is segmented into distinct sequential stages: first forming the lower gate structure with its specific materials and geometry, then removing sacrificial protective layer material, and finally forming the upper gate structure with different materials and geometry. This segmentation enables independent optimization of each gate structure without mutual interference.
Solution Approach 2:
Different gate structures are created at different locations (upper vs. lower channel regions) with locally optimized properties. The lower gate can have one composition and geometry while the upper gate has another, allowing each to be tailored for its specific functional requirements without constraining the other.
Data Source
AI summary
A stacked transistor architecture has a fin structure that includes lower and upper portions separated by an isolation region built into the fin structure. Upper and lower gate structures on respective upper and lower fin structure portions may be different from one another (e.g., with respect to work function metal and/or gate dielectric thickness). One example methodology includes depositing lower gate structure materials on the lower and upper channel regions, recessing those materials to re-expose the upper channel region, and then re-depositing upper gate structure materials on the upper channel region. Another example methodology includes depositing a sacrificial protective layer on the upper channel region. The lower gate structure materials are then deposited on both the exposed lower channel region and sacrificial protective layer. The lower gate structure materials and sacrificial protective layer are then recessed to re-expose upper channel region so that upper gate structure materials can be deposited.