Stacked Transistor Gate Stack Formation Sequence
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Solution Overview
Problem
The vertical stacking of transistors in integrated circuits poses challenges as high-temperature processes used for forming upper transistors can cause uncontrolled thickening of the gate dielectric and work function shifts in lower transistors, degrading their performance and limiting the use of certain CMOS technologies.
Innovation Solution
The gate stack for both upper and lower transistors is formed after completing the processing for the upper transistor, avoiding any impact on the lower transistor's gate stack and allowing for the use of high-temperature processes without risking dielectric growth or work function shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If high-temperature processes are used for forming upper transistors, then transistor formation is enabled, but gate dielectric thickening and work function shifts occur in lower transistors
Solution Approach 1:
The fabrication process is divided into two distinct sequences: (1) form lower transistor structures including gate stack, then form upper transistor structures; or (2) form upper transistor structures first, then form lower transistor gate stack. This segmentation allows high-temperature processes to be applied to one transistor level without affecting the gate dielectric of the other level, as the gate stack is either already formed and protected or not yet formed and thus not susceptible to damage.
Solution Approach 2:
The gate stack for lower transistors is formed in advance before upper transistor processing, or alternatively, the gate stack formation is delayed until after upper transistor processing is complete. This preliminary action ensures that the gate dielectric is either already formed and can be protected during subsequent high-temperature processing, or is not yet formed and thus cannot be damaged by such processing.
2Ease of manufacture
If high-temperature processes are used for forming upper transistors, then transistor formation is enabled, but work function shifts occur in lower transistors
Solution Approach 1:
The fabrication process is divided into two distinct sequences: (1) form lower transistor structures including gate stack, then form upper transistor structures; or (2) form upper transistor structures first, then form lower transistor gate stack. This segmentation allows high-temperature processes to be applied to one transistor level without affecting the gate stack of the other level, thereby preventing work function shifts and maintaining lower transistor performance.
Solution Approach 2:
The gate stack for lower transistors is formed in advance before upper transistor processing, or alternatively, the gate stack formation is delayed until after upper transistor processing is complete. This preliminary action ensures that the gate stack is either already formed and can be protected during subsequent high-temperature processing, or is not yet formed and thus cannot be damaged by such processing, thereby maintaining transistor reliability.
Data Source
AI summary
Integrated circuits with stacked transistors and methods of manufacturing the same are disclosed. An example integrated circuit includes a first transistor in a first portion of the integrated circuit, and a second transistor stacked above the first transistor and in a second portion of the integrated circuit above the first portion. The integrated circuit further includes a bonding layer between the first and second vertical portions of the integrated circuit. The bonding layer includes an opening extending therethrough between the first and second vertical portions of the integrated circuit. The integrated circuit also includes a gate dielectric on an inner wall of the opening.