Stacked Transistor Connection Structure for Dense IC Routing
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Solution Overview
Problem
The optimization of metal routing in integrated circuits to achieve better transistor density and efficiency is a significant challenge, particularly with the use of buried power rails and transistors of different depths.
Innovation Solution
The implementation of a connection layer and an isolation layer between stacked transistors, which allows for efficient routing without increasing the active area width or gate density, and enables connectivity between P and N type epitaxial layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If contacts are arranged beside active areas to provide routing connectivity, then routing feasibility is improved, but active area width and gate density increase
Solution Approach 1:
The patent moves the routing connection from the lateral dimension (beside active areas) to the vertical dimension (through the substrate). Connection layers are formed at different depths below the active areas, allowing routing connectivity without increasing the planar footprint of the active region. This dimensional transition resolves the contradiction by providing routing access in the depth direction rather than expanding the width.
Solution Approach 2:
The connection layers are nested within the substrate structure, positioned at different depths below the active areas. Multiple connection layers can be stacked vertically, with each layer providing routing connectivity at its specific depth level. This nesting approach allows comprehensive routing connectivity while maintaining a compact active area footprint, as the connections are embedded within the existing substrate volume rather than expanding outward.
2Ease of operation
If more metal routing layers are added to improve connectivity, then routing effectiveness is improved, but device complexity increases
Solution Approach 1:
The routing connectivity function is segmented into multiple discrete connection layers positioned at different depths within the substrate. Each connection layer handles specific routing connections at its depth level, rather than requiring all routing to occur in a single complex metal layer. This segmentation of the routing function across vertical layers reduces the complexity of individual routing layers while maintaining overall routing effectiveness.
Solution Approach 2:
The connection layers act as intermediary structures between the active areas and the external routing network. Rather than directly complexifying the metal routing layers, the patent introduces these intermediate connection layers that simplify the interface between the active region and the routing network, thereby reducing overall device complexity while improving routing effectiveness.
3Productivity
If buried power rails are used to reduce cell height, then transistor density is improved, but metal routing optimization becomes more difficult
Solution Approach 1:
The patent compensates for the constrained horizontal routing space (caused by reduced cell height from buried power rails) by utilizing the vertical dimension. Connection layers are positioned at multiple depths below the active areas, creating additional routing pathways in the depth direction. This allows high transistor density to be maintained while routing complexity is managed through vertical rather than horizontal expansion.
Data Source
AI summary
An integrated circuit is provided, including a first transistor of a first conductivity type comprising first and second active regions, a second transistor of a second conductivity type comprising third and fourth active regions and arranged under the first transistor along a first direction, a first gate structure extending in the first direction and shared by the first and second transistors, an isolation layer sandwiched between the first and second transistors and extending along a second direction to pass through the first gate structure, and a connection layer surrounded by the isolation layer and extending along the second direction to pass through the first gate structure. The isolation layer has a first surface contacting the first and second active regions and a second surface contacting the third and fourth active regions. The connection layer comprises first and second portions are electrically coupled to the first and fourth active regions.