Stacked Transistor Insulating Layer Thickness Control
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Solution Overview
Problem
The challenge in display device manufacturing is to increase transistor density and aperture ratio while minimizing additional processing stages, especially when transistors are formed on different layers, which requires precise control of insulating layer thicknesses to optimize heat transfer and prevent substrate damage during activation and crystallization.
Innovation Solution
A display device structure with specific thickness differences between insulating layers to control heat distribution, allowing for selective activation of semiconductor layers without damaging the substrate, and a manufacturing method involving the formation of polysilicon semiconductor layers with controlled thicknesses and crystallization techniques like excimer laser annealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are stacked on different layers to increase transistor density, then transistor density increases and aperture ratio increases, but additional processing stages are required
Solution Approach 1:
The patent transitions from planar transistor arrangement to three-dimensional stacked structure, placing transistors on different layers (first transistor on first substrate, second transistor on second substrate). This dimensional change increases transistor density without requiring additional processing stages within the same layer, as each transistor operates independently on its own substrate layer.
2Use of energy by moving object
If insulating layer thickness is reduced to improve heat transfer, then crystallization efficiency improves, but substrate damage risk increases
Solution Approach 1:
The patent applies different thickness specifications to different insulating layers based on their specific functions. The first insulating layer (between first semiconductor layer and first gate electrode) has thickness of 50-150 nm optimized for heat transfer during crystallization, while the second insulating layer (between second semiconductor layer and second gate electrode) has thickness of 150-300 nm providing enhanced protection. This local differentiation allows optimal heat transfer where needed while preventing substrate damage in critical regions.
Solution Approach 2:
The patent introduces the second insulating layer with greater thickness (150-300 nm) as a protective cushion between the second semiconductor layer and the second substrate. This pre-established protective layer prevents direct thermal damage to the substrate during the crystallization process, absorbing excess heat before it reaches the substrate while still allowing sufficient heat transfer for effective crystallization.
3Reliability
If insulating layer thickness is increased to protect substrate, then substrate integrity is maintained, but heat transfer for crystallization is reduced
Solution Approach 1:
The patent optimizes insulating layer thickness locally for each transistor structure. The first insulating layer is kept thin (50-150 nm) to ensure efficient heat transfer for crystallization of the first semiconductor layer, while the second insulating layer is thicker (150-300 nm) to provide substrate protection for the second transistor. This localized optimization allows each layer to fulfill its primary function without compromising the other.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of transistors by minimizing additional processing stages, improving heat transfer for effective crystallization, and maintaining substrate integrity, thereby increasing transistor density and aperture ratio without damaging the substrate.
Implementation Method 1
forming an amorphous silicon layer and crystallizing amorphous silicon in the amorphous silicon layer
Implementation Method 2
crystallizing amorphous silicon in the amorphous silicon layer
Implementation Method 3
the first semiconductor layer is activated or annealed when the crystallization is performed
Data Source
AI summary
A display device includes a substrate, a buffer layer on the substrate, a first semiconductor layer of a first transistor on the buffer layer, a first insulating layer disposed on the first semiconductor layer, a first gate electrode of the first transistor on the first insulating layer, a second insulating layer on the first gate electrode, and a second semiconductor layer of a second transistor disposed on the second insulating layer. A difference between a first distance between a lower side of the buffer layer and an upper side of the second insulating layer and a second distance between an upper side of the first semiconductor layer and an upper side of the second insulating layer is 420 to 520 angstroms.