Stacked Transistor Integrated Insulator for Thick Defect-Reduced Isolation
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Solution Overview
Problem
Existing integrated circuit devices face challenges in forming thick integrated insulators with a single layer, which are beneficial in reducing defects during transistor formation, but are difficult to achieve.
Innovation Solution
The integration of a stacked transistor structure with an integrated insulator comprising multiple layers of different materials, where the outer layer extends between the inner layer and the gate electrodes, facilitating defect reduction and enabling a thickness of at least 10 nanometers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single layer is used for the integrated insulator, then the manufacturing process is simpler, but it is difficult to achieve the required thickness of at least 10 nanometers without increasing defects
Solution Approach 1:
The integrated insulator is divided into multiple layers (first integrated insulator layer and second integrated insulator layer) with different materials. This segmentation allows each layer to be optimized for specific functions: the first layer provides a foundation while the second layer achieves the required total thickness of at least 10 nanometers. By dividing the insulator into segments, the patent achieves the target thickness without the defects that would arise from forming a single thick layer.
Solution Approach 2:
The patent employs composite materials by using different materials for the first and second integrated insulator layers. This composite structure enables each layer to contribute different properties: one material may provide better adhesion or defect reduction while the other achieves the required thickness. The composite approach resolves the contradiction by combining materials with complementary characteristics to achieve both manufacturability and precision.
2Reliability
If a thick integrated insulator is formed to reduce defects, then device reliability improves, but forming such a thick insulator with a single layer is difficult to achieve
Solution Approach 1:
The thick integrated insulator (at least 10 nanometers) is segmented into multiple formable layers. Each individual layer can be formed within the capabilities of existing manufacturing processes, avoiding the difficulty of forming a single thick layer. The segmentation maintains the total thickness required for defect reduction while making the formation process achievable through standard fabrication techniques.
Solution Approach 2:
The first integrated insulator layer is formed as a preliminary action before forming the second layer. This preliminary layer provides a foundation that facilitates the subsequent formation of the second layer, enabling the achievement of total thickness required for reliability. The step-by-step preliminary actions make the overall thick insulator formation manufacturable.
Data Source
Figure 1
Figure 1A~1B
Figure 1C~1D
AI summary
An integrated circuit device comprises an upper transistor that is on a substrate. The upper transistor comprises an upper channel region (108). The integrated circuit device further comprises a lower transistor that is between the substrate and the upper transistor. The lower transistor comprises a lower channel region (106). The integrated circuit device further includes an integrated insulator (126) that is between the lower channel region and the upper channel region. The integrated insulator comprises an outer layer (129) and an inner layer (127) in the outer layer, wherein the inner layer and the outer layer comprise different materials.