Stacked Transistor Intergate Spacer for Lower Channel Integrity
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Solution Overview
Problem
The existing stacked transistor structures in integrated circuit devices face performance degradation due to recessed or pinched-off regions formed during the formation of work function layers, which affect the lower transistor's performance.
Innovation Solution
The integrated circuit device includes a stacked transistor structure with an upper transistor and a lower transistor, where an intergate spacer made of insulating material is placed adjacent to the side surface of the lower channel region, and a lower work function layer is formed between the lower channel region and the intergate spacer, improving the performance by reducing recessed or pinched-off regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If work function layers are formed in stacked transistor structures, then the transistor performance can be improved, but recessed or pinched-off regions are formed during the formation process which degrade the lower transistor's performance
Solution Approach 1:
An intergate spacer is introduced as an intermediary structure between the upper and lower transistors. This spacer physically separates the two transistors and prevents the formation of recessed or pinched-off regions in the lower transistor during work function layer formation, thereby maintaining manufacturing precision while still allowing performance improvement through proper work function layer placement
Solution Approach 2:
The gate structure is segmented into upper and lower portions with the intergate spacer creating a physical division. This segmentation allows independent optimization of each transistor's work function layer formation process, preventing the harmful interactions that cause recessed regions while maintaining the benefits of stacked transistor architecture
2Productivity
If stacked transistor structures are implemented to increase integration density, then more transistors can be packed in the same area, but the formation of recessed or pinched-off regions during work function layer formation degrades device performance
Solution Approach 1:
The intergate spacer acts as a mediator structure that enables high integration density through stacked transistor configuration while simultaneously preventing the formation of recessed or pinched-off regions. By introducing this intermediary element, the patent achieves both high productivity (integration density) and high reliability (device performance)
Solution Approach 2:
The intergate spacer provides localized structural support and separation specifically where needed between the upper and lower transistors. This local quality enhancement prevents harmful recessed regions in critical areas while maintaining the overall stacked structure for high integration density
Data Source
Figure 1
Figure 1A~1B
Figure 1C~1D
AI summary
An integrated circuit device may comprise an upper transistor on a substrate. The upper transistor may comprise an upper channel region. The integrated circuit device may further comprise a lower transistor between the substrate and the upper transistor. The lower transistor may comprise a lower channel region, an intergate spacer comprising an insulating material and adjacent to a side surface of the lower channel region, and a gate layer. The intergate spacer may be between the side surface of the lower channel region and the gate layer.