Stacked Transistor Isolation Structure for Defect-Selective CFET Etching
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Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, challenges arise in maintaining device performance and manufacturing ease due to increased complexity and defect risks.
Innovation Solution
The formation of complementary field-effect transistors (CFETs) with a lower nanostructure-FET and an upper nanostructure-FET, utilizing an isolation structure between them. This isolation structure is created by initially forming a dummy nanostructure in a multi-layer stack, which is then partially replaced with the isolation material, often doped silicon, to reduce defect generation and enhance etch selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but defect risks and manufacturing complexity increase
Solution Approach 1:
The patent applies preliminary action by forming a dummy nanostructure before the final isolation structure. This dummy structure serves as a placeholder that guides subsequent processing steps, ensuring proper alignment and positioning of the isolation material. The dummy nanostructure is removed after serving its guiding purpose, leaving a clean isolation region without defects
Solution Approach 2:
The dummy nanostructure acts as an intermediary element during the fabrication process. It mediates between the patterning step and the isolation structure formation, providing a temporary reference structure that enables precise material deposition and subsequent removal without directly affecting the final device performance
2Reliability
If conventional isolation structures are used in stacked transistors, then device isolation is achieved, but etch selectivity deteriorates and defects increase
Solution Approach 1:
The patent changes the physical and chemical parameters of the dummy nanostructure by using doped silicon with specific crystal orientations. This parameter change enables the dummy structure to exhibit different etch rates compared to surrounding materials, providing the necessary etch selectivity for precise isolation structure formation without compromising device isolation
Solution Approach 2:
The invention applies local quality by creating a dummy nanostructure with specific local properties (doping concentration, crystal orientation) that differ from the surrounding semiconductor layers. This localized differentiation enables selective etching at the isolation region while preserving the integrity of adjacent active device regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance and manufacturing ease by reducing defects and maintaining good etch selectivity, thereby enabling more efficient integration of electronic components in a given area.
Implementation Method 1
The isolation structure may be formed by initially forming a dummy nanostructure in a multi-layer stack, and then at least partially replacing the dummy nanostructure with the isolation structure after subsequent processing of the multi-layer stack. In some embodiments, the dummy nanostructure is formed of doped silicon
Data Source
AI summary
In an embodiment, a method includes: patterning a lower semiconductor nanostructure, an upper semiconductor nanostructure, and a dummy nanostructure, the dummy nanostructure disposed between the lower semiconductor nanostructure and the upper semiconductor nanostructure, the dummy nanostructure including doped silicon; forming an opening between the lower semiconductor nanostructure and the upper semiconductor nanostructure by etching the doped silicon of the dummy nanostructure; forming an isolation structure in the opening; and depositing a gate dielectric around the isolation structure, the upper semiconductor nanostructure, and the lower semiconductor nanostructure.