Stacked Transistor Isolation Structure for Defect-Selective Etching
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in maintaining device performance and manufacturing ease due to defects and lattice mismatch in vertically stacked transistors.
Innovation Solution
The formation of a superlattice structure comprising alternating layers of silicon-germanium and a strain-compensating material as a dummy nanostructure, which is later replaced with an isolation structure, enhances etch selectivity and reduces the risk of defects, thereby improving device performance and manufacturing efficiency in complementary field-effect transistors (CFETs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but defects and lattice mismatch increase
Solution Approach 1:
A dummy nanostructure is formed in advance between the first and second semiconductor nanostructures before the final device assembly. This dummy structure serves as a placeholder that is later replaced with an isolation structure, allowing the etching process to be optimized for the dummy material rather than the semiconductor material itself, thereby reducing defects in the final device
Solution Approach 2:
The patent changes the material parameter of the dummy nanostructure to a composition different from the semiconductor nanostructures (e.g., different germanium concentration in silicon-germanium). This parameter difference enables selective etching where the dummy structure can be removed without damaging the semiconductor nanostructures, solving the lattice mismatch problem while maintaining high integration density
2Manufacturing precision
If etching process is optimized for high selectivity, then dummy nanostructure can be removed precisely, but manufacturing complexity increases
Solution Approach 1:
The dummy nanostructure acts as an intermediary element that facilitates the manufacturing process. By using a material with distinct etching properties, the dummy structure enables selective removal without requiring complex masking or multiple etching steps, thereby achieving high manufacturing precision while actually simplifying the overall process
Solution Approach 2:
The patent segments the manufacturing process into distinct phases: forming the dummy nanostructure, performing selective etching to remove only the dummy material, and then forming the isolation structure. This segmentation allows each step to be optimized independently, achieving high precision without excessive complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of defects and lattice mismatch, enhancing the performance and ease of manufacturing of vertically stacked transistors by providing improved etch selectivity and isolation in CFETs.
Implementation Method 1
challenges arise in maintaining device performance and manufacturing ease due to defects and lattice mismatch in vertically stacked transistors
Implementation Method 2
a superlattice structure comprising alternating layers of silicon-germanium and a strain-compensating material
Data Source
AI summary
Methods of forming a stacked transistor are provided. One representative method may include patterning a first dummy nanostructure, a second dummy nanostructure, and a semiconductor nanostructure. The semiconductor nanostructure may be disposed between the first dummy nanostructure and the second dummy nanostructure. The first dummy nanostructure may comprise a first semiconductor material and the second dummy nanostructure may comprise a superlattice structure. The representative method may also include performing an etching process that simultaneously recesses the first dummy nanostructure to form a sidewall recess and removes the second dummy nanostructure to form an opening. The etching process selectively etches the superlattice structure at a faster rate than the first semiconductor material. The representative method may further include forming an inner spacer and an isolation structure in, respectively, the sidewall recess and the opening.