Bilayer Isolation Layers for Stacked Transistor Source/Drain Epi
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Solution Overview
Problem
The fabrication of complementary field-effect transistors (CFETs) faces challenges in properly isolating source/drain epitaxial structures between vertically stacked transistors, which affects the performance and density of transistors in chip designs, particularly in gate-all-around (GAA) FETs and finFETs.
Innovation Solution
The implementation of a bilayer isolation structure comprising an oxygen-free bottom layer and a low-k top layer, deposited and etched to ensure adequate protection and spacing between the S/D epitaxial structures, using processes like PECVD and PEALD for the bottom layer and CVD for the top layer, with post-deposition treatments to optimize thickness and prevent oxidation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer isolation structure is used, then the manufacturing process is simpler, but the protection against oxidation and isolation effectiveness are insufficient
Solution Approach 1:
The isolation structure is divided into two distinct layers: a first dielectric layer (e.g., silicon nitride) providing oxidation protection, and a second dielectric layer (e.g., silicon oxide) providing isolation and low-k properties. This segmentation allows each layer to perform its specialized function optimally, resolving the contradiction between manufacturing simplicity and oxidation protection reliability.
Solution Approach 2:
The patent employs a composite bilayer isolation structure combining different dielectric materials with complementary properties. The first layer uses materials like silicon nitride for oxidation barrier properties, while the second layer uses silicon oxide or low-k materials for isolation effectiveness. This composite approach achieves both protection and isolation goals that a single material cannot satisfy.
2Reliability
If the isolation layer thickness is increased, then oxidation protection and isolation effectiveness improve, but parasitic capacitance increases
Solution Approach 1:
The bilayer structure applies different dielectric materials with different k-values in different regions (layers). The first layer provides oxidation protection with appropriate thickness, while the second layer provides isolation with low-k properties to minimize parasitic capacitance. This local differentiation of material properties allows simultaneous achievement of isolation effectiveness and low parasitic capacitance.
Solution Approach 2:
The patent optimizes the thickness parameters of each layer independently. The first dielectric layer thickness is optimized for oxidation protection (typically thinner), while the second dielectric layer thickness is optimized for isolation effectiveness while maintaining low parasitic capacitance (typically thicker but with lower k-value). This parameter optimization resolves the contradiction between isolation effectiveness and parasitic capacitance reduction.
3Reliability
If PECVD/PEALD processes are used for the bottom layer, then oxidation protection is enhanced, but manufacturing complexity increases
Solution Approach 1:
The first dielectric layer is deposited using PECVD or PEALD processes to provide preliminary oxidation protection before subsequent processing steps. This preliminary action prevents oxidation of the underlying semiconductor structures during later fabrication steps, justifying the enhanced process complexity by preventing defects and ensuring device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively isolates the S/D epitaxial structures, reducing parasitic capacitance and cross-talk between transistors, thereby enhancing transistor density and performance while maintaining the active area footprint.
Implementation Method 1
depositing an oxygen-free dielectric in an opening over a first epitaxial structure
Implementation Method 2
exposing the oxygen-free dielectric to an oxidizing process to oxidize the oxygen-free dielectric
Implementation Method 3
etching the oxidized oxygen-free dielectric material
Implementation Method 4
using processes like PECVD and PEALD for the bottom layer and CVD for the top layer
Data Source
AI summary
The present disclosure is directed to a method for the fabrication of isolation structures between source/drain (S/D) epitaxial structures of stacked transistor structures. The method includes depositing an oxygen-free dielectric material in an opening over a first epitaxial structure, where the oxygen-free dielectric material covers top surfaces of the first epitaxial structure and sidewall surfaces of the opening. The method also includes exposing the oxygen-free dielectric material to an oxidizing process to oxidize the oxygen-free dielectric material so that the oxidizing process does not oxidize a portion of the oxygen-free dielectric material on the first epitaxial structure. Further, etching the oxidized oxygen-free dielectric material and forming a second epitaxial layer on the oxygen-free dielectric material not removed by the etching to substantially fill the opening.