Stacked Transistor Structure With Laser Reflection Thermal Shielding
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Solution Overview
Problem
As CMOS scaling reaches physical limits in the 2-D plane, stacked transistor structures face challenges due to thermal budget impacts on lower transistor device integrity from subsequent top transistor processes, necessitating a solution for low-temperature device formation without adverse thermal effects.
Innovation Solution
Incorporating a laser reflection layer between logic device layers in a stacked transistor structure, enabling nanosecond laser annealing for dopant activation, which allows for low-temperature processing that improves top layer transistor performance without affecting the bottom layer, facilitating vertically stacked CMOS device structures with increased density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional high-temperature processing is used for top transistor formation, then dopant activation and device performance are improved, but thermal damage occurs to lower transistor layers
Solution Approach 1:
A laser reflection layer is introduced as an intermediary component between the top and bottom transistor layers. This reflection layer selectively reflects laser energy back toward the top layer during laser annealing, enabling dopant activation in the top transistor without transmitting excessive thermal energy to the bottom transistor layer, thus preventing thermal damage while maintaining device performance
Solution Approach 2:
The patent utilizes selective laser annealing with controlled parameters (wavelength, pulse duration, energy density) to achieve dopant activation at lower temperatures compared to conventional processing. By optimizing these parameters, the top transistor receives sufficient energy for dopant activation while the bottom layer remains below damage thresholds, resolving the thermal contradiction
2Productivity
If CMOS scaling continues in the 2-D plane, then integration density improves, but physical limits are approached
Solution Approach 1:
The patent transitions from 2-D planar CMOS scaling to 3-D vertically stacked transistor architecture. By stacking multiple transistor layers along the vertical dimension, the device achieves higher integration density without further lateral downsizing, effectively overcoming the physical limits of 2-D scaling while maintaining manufacturability through selective laser annealing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of dense and high-performance 3D stacked-FET architectures with successive layer building along the Z-axis direction, maintaining the integrity of lower transistor layers and expanding process windows for stacked FET devices.
Implementation Method 1
laser reflection layer on the first transistor
Implementation Method 2
enabling nanosecond laser annealing for dopant activation
Data Source
AI summary
A semiconductor device is provided and includes a first substrate including a first transistor; a laser reflection layer on the first transistor; and a second substrate on the laser reflection layer, the second substrate including a second transistor.