Stacked Transistor Layout with Angled Bodies for Contact Routing
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Solution Overview
Problem
Conventional semiconductor device layouts face challenges in scaling down transistor dimensions due to complexities in routing electrical contacts, especially when NMOS and PMOS transistors are stacked, making it difficult to maintain adequate spacing and establish effective contacts to buried transistors.
Innovation Solution
A stacked transistor layout is introduced where CMOS transistors are oriented at different angles, allowing for efficient scaling by stacking them on top of each other, with interconnects and contacts designed to facilitate efficient routing and manufacturing, utilizing semiconductor fins and dielectric materials to enable smaller, more integrated devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If transistor bodies are arranged parallel with contacts running orthogonally, then routing of electrical contacts becomes manageable, but scaling down transistor dimensions becomes limited due to inadequate spacing
Solution Approach 1:
The patent transitions from a two-dimensional parallel arrangement of transistor bodies to a three-dimensional stacked configuration where transistor bodies are arranged vertically on top of each other. This dimensional change allows contacts to be routed horizontally at different levels, resolving the spacing limitation while maintaining manufacturability through standardized vertical stacking processes.
Solution Approach 2:
The patent implements nested stacking where smaller transistor structures are positioned within or adjacent to larger ones in the vertical dimension. Multiple transistor bodies are nested in layers, with each layer containing complete transistor structures, enabling dense integration while preserving contact routing pathways at each level.
2Area of stationary object
If NMOS and PMOS transistor bodies are stacked directly on top of each other, then footprint efficiency improves, but establishing contacts to buried transistors becomes prohibitively difficult
Solution Approach 1:
The patent segments the stacked transistor structure into distinct layers with intermediate dielectric regions. Each transistor body is separated by insulating layers, creating discrete contact zones. This segmentation allows independent contact formation to each transistor body without interference from adjacent structures, solving the contact establishment problem while maintaining high footprint efficiency.
Solution Approach 2:
The patent introduces intermediate dielectric layers and contact holes as mediators between stacked transistor bodies. These intermediary structures provide controlled pathways for electrical contacts to reach buried transistors, enabling precise contact formation while maintaining the compact vertical stacking arrangement for optimal footprint efficiency.
Data Source
AI summary
An apparatus is provided which comprises: a first transistor body comprising one or more semiconductor materials and having a length comprising a source region and a drain region with a channel region therebetween, a first dielectric layer over the first transistor body, a second transistor body comprising one or more semiconductor materials and having a length comprising a source region and a drain region with a channel region therebetween, wherein the second transistor body is over the first dielectric layer and wherein the length of the second transistor body is non-parallel to the length of the first transistor body, and a gate coupled with the channel regions of both the first transistor body and the second transistor body. Other embodiments are also disclosed and claimed.