Stacked Transistor Interconnect Layout for Lower Device Access
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Solution Overview
Problem
Current stacked transistor configurations face challenges in efficiently connecting lower source or drain regions to frontside interconnect structures, particularly due to the complexity of vertical and horizontal conductive interconnect features, which affects the integration and performance of three-dimensional integrated circuits.
Innovation Solution
The implementation of a vertically stacked transistor architecture that utilizes a combination of horizontal and vertical conductive interconnect features, including conductive vias and backside interconnect structures, to facilitate connections between the lower source or drain regions and the frontside interconnect structure, enabling effective access and integration of upper and lower devices within the integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked transistor architecture is implemented to increase transistor density, then transistor density is improved, but device complexity increases due to the need for both vertical and horizontal conductive interconnect features to access lower source/drain regions
Solution Approach 1:
The interconnect structure is segmented into distinct functional components: upper device interconnects accessed from the front surface, and lower device interconnects accessed from the back surface. This segmentation allows independent optimization of each interconnect path, reducing overall complexity while maintaining high transistor density through vertical stacking.
Solution Approach 2:
The patent transitions from planar (2D) interconnect access to three-dimensional (3D) access by utilizing both front and back surfaces of the stacked device structure. This dimensional change enables lower source/drain regions to be accessed from the back surface, eliminating the need for complex through-silicon vias or lengthy horizontal interconnects that would traverse through the upper device.
2Reliability
If lower source or drain regions are accessed through vertical conductive interconnect features traversing the height of upper and lower devices, then connectivity is achieved, but manufacturing precision requirements increase
Solution Approach 1:
Instead of accessing lower device regions from the front surface (conventional approach), the patent inverts the access direction by contacting lower source/drain regions from the back surface. This inversion eliminates the need for vertical interconnects to traverse through the upper device, thereby reducing alignment precision requirements and avoiding potential damage to the upper device during fabrication.
3Quantity of substance
If stacked transistor configuration is used to expand transistor density in z-dimension, then transistor density is improved, but ease of operation deteriorates due to difficulty in accessing lower device regions
Solution Approach 1:
The patent utilizes the back surface of the substrate as an additional access dimension for lower device regions. By forming contact holes and conductive interconnects on the back surface, lower source/drain regions become easily accessible without requiring complex lateral routing or deep vertical vias through the upper device, thereby improving ease of operation while maintaining high transistor density.
Data Source
AI summary
An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.