Stacked Transistor Memory Cells on Opposite Substrate Sides
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Solution Overview
Problem
Down-scaling memory cells in DRAM and eDRAM integrated circuits is challenging due to the requirement for low leakage current in access transistors, as reducing gate length increases leakage current exponentially, causing memory cells to lose charge quickly.
Innovation Solution
The integration of stacked transistors and memory cells on opposite sides of a semiconductor substrate, with aligned gate lengths and capacitors, allows for increased memory cell density without adverse effects on leakage current, enabling double the memory cell density per unit area while maintaining charge retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If gate length is reduced to down-scale transistors in DRAM and eDRAM integrated circuits, then memory cell size is reduced, but leakage current increases exponentially
Solution Approach 1:
The patent transitions from planar transistor arrangement to a three-dimensional stacked configuration where transistors are positioned on opposite sides of a semiconductor substrate and coupled through vertical interconnects. This dimensional change allows memory cells to be stacked vertically, achieving higher density without reducing gate length, thereby maintaining low leakage current while increasing storage capacity.
2Quantity of substance
If gate length is reduced to down-scale transistors, then memory cell density increases, but charge retention time decreases
Solution Approach 1:
By stacking transistors vertically on opposite sides of the substrate and connecting them through vertical interconnect structures, the patent achieves increased memory cell density without compromising the gate length. This maintains the electrical characteristics necessary for charge retention while accommodating more memory cells per unit area.
3Quantity of substance
If stacked transistors are integrated on opposite sides of semiconductor substrate, then memory cell density per unit area increases, but device complexity increases
Solution Approach 1:
The patent divides the memory structure into two separate sides of the semiconductor substrate, with transistors formed on each side and coupled through vertical interconnects. This segmentation allows independent optimization of each transistor while achieving high density through the stacked configuration, managing complexity through modular design.
Solution Approach 2:
The semiconductor substrate serves multiple functions: it provides mechanical support, electrical isolation between stacked transistors, and a platform for forming both transistors on opposite sides. The vertical interconnect structures serve dual purposes of electrical connection and structural alignment, reducing overall device complexity despite the three-dimensional configuration.
Data Source
AI summary
Embodiments of the present disclosure describe an integrated circuit that may include a first transistor on a first side of a semiconductor substrate and a second transistor on a second side of the semiconductor substrate, wherein the second side is opposite and parallel to the first side. In embodiments, the integrated circuit may further include a first capacitor positioned on the first side of the semiconductor substrate and coupled to the first transistor to form a first memory cell, and a second capacitor positioned on the second side of the semiconductor substrate and coupled to the second transistor to form a second memory cell.