Stacked Transistor Semiconductor Memory Device with Overlapping Power Supply Wiring
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in achieving reduced area, higher operating speed, lower power consumption, smaller power supply voltage variation, and reduced manufacturing costs while integrating multiple transistors effectively.
Innovation Solution
A semiconductor device design featuring stacked p-channel and n-channel transistors with oxide semiconductor and silicon channel formation regions, where the transistors are arranged and wired with overlapping power supply conductors to minimize area and enhance operating speed, and using adjacent conductor layers to increase wiring capacitance and reduce power supply noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If transistors are arranged in stacked configuration with overlapping power supply conductors, then area is reduced, but device complexity increases
Solution Approach 1:
The patent transitions from planar transistor arrangement to three-dimensional stacked configuration, where first and second transistors are positioned at different vertical levels. Power supply conductors extend in overlapping regions between transistor components, utilizing the third dimension to reduce lateral area while maintaining electrical connectivity.
Solution Approach 2:
The patent implements nested arrangement where power supply conductors are positioned within the vertical space occupied by transistor structures. The first and second conductors are embedded in insulating layers that are integrated within the transistor stack, allowing conductors to occupy the same horizontal footprint as transistor components.
2Object-affected harmful factors
If adjacent conductor layers are used to increase wiring capacitance, then power supply noise is reduced, but device area increases
Solution Approach 1:
The patent reduces power supply noise by utilizing vertical stacking of conductor layers rather than lateral expansion. First and second power supply conductors are positioned in adjacent vertical layers with overlapping horizontal projections, creating capacitance through vertical proximity while maintaining compact lateral dimensions.
3Speed
If oxide semiconductor and silicon channel formation regions are used in stacked transistors, then operating speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs different semiconductor materials for different transistor types: oxide semiconductor for the first transistor and silicon for the second transistor. Each material is selected to optimize the electrical characteristics of its respective transistor, with oxide semiconductor providing low off-state current and silicon providing high mobility, thereby improving overall operating speed through localized material optimization.
Data Source
AI summary
A semiconductor device including a circuit that has a reduced area is provided. Alternatively, a semiconductor device including a circuit that can have a smaller power supply voltage variation is provided.The semiconductor device includes a first transistor, a second transistor, a first power supply wiring, and a second power supply wiring. The first transistor and the second transistor are stacked. The first power supply wiring and the second power supply wiring are stacked. The second power supply wiring and the first power supply wiring at least partly overlap with each other. The second power supply wiring and the first power supply wiring are substantially parallel to each other. A source electrode of the first transistor is electrically connected to the first power supply wiring. A source electrode of the second transistor is electrically connected to the second power supply wiring. The second transistor is an n-channel transistor, and a channel formation region is formed using an oxide semiconductor. The first transistor is a p-channel transistor, and a channel formation region is formed using silicon.