Stacked Vertical Transistor Memory Cell Epi Connections
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Solution Overview
Problem
Current semiconductor technologies face challenges in reducing contact poly pitch and increasing efficiency in stacked vertical transistor memory cells, particularly in aligning ohmic contacts and channels vertically to enhance current flow and contact density.
Innovation Solution
A stacked transistor memory cell design is implemented, featuring a bottom tier with n-type field-effect transistors and a top tier with p-type field-effect transistors, utilizing epitaxial region connections and gate-to-epi connections between tiers to create a cross-coupling structure, including floating and non-floating transistors with electrically disconnected terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical transistor orientation is used to reduce contact poly pitch and increase contact density, then efficiency is improved, but device complexity increases due to the need for precise vertical alignment of ohmic contacts and channels
Solution Approach 1:
The patent transitions from lateral transistor orientation to vertical orientation, utilizing the third dimension (vertical stacking) to increase contact density. By stacking transistors vertically with ohmic contacts aligned in the vertical direction, the design achieves higher contact density per unit surface area while managing alignment complexity through the vertical dimension rather than lateral positioning.
Solution Approach 2:
The patent merges multiple transistor tiers (bottom tier with nFETs and top tier with pFETs) into a single vertical stack, combining their functions in a compact structure. The shared merged epi regions and cross-coupling connections integrate the tiers, reducing the overall footprint while maintaining high contact density through vertical alignment.
2Area of stationary object
If stacked vertical transistor tiers are implemented to reduce unit cell size, then area efficiency is improved, but manufacturing precision requirements increase for epi connections and gate alignment
Solution Approach 1:
The patent segments the transistor structure into distinct tiers (bottom tier with nFETs, top tier with pFETs) separated by intermediate dielectric layers. This segmentation allows for modular manufacturing where each tier can be formed and aligned independently, reducing the cumulative precision requirements compared to forming all connections in a single complex step.
Solution Approach 2:
The patent introduces merged epitaxial regions and cross-coupling connection structures as intermediary elements between tiers. These intermediaries serve as alignment references and connection points that simplify the manufacturing process by providing fixed geometric relationships between tiers, thereby reducing the precision requirements for direct gate-to-gate alignment.
3Area of stationary object
If cross-coupling with epi connections is used between tiers to achieve tighter circuit packing, then area efficiency is improved, but wire length in back-end-of-the-line increases
Solution Approach 1:
The patent utilizes vertical stacking to achieve tight circuit packing in the lateral plane by moving connections to the vertical dimension. The cross-coupling connections between tiers are formed through vertical epi regions rather than lateral wire routing, effectively trading lateral wire length for vertical connection height, thereby improving area efficiency while managing wire length through 3D routing.
4Adaptability or versatility
If floating transistors with electrically disconnected terminals are implemented, then circuit functionality is improved, but device complexity increases
Solution Approach 1:
The patent implements floating transistors that can serve multiple functions depending on their connection state. The same transistor structure can function as a regular connected transistor or as a floating transistor with electrically disconnected terminals, providing circuit functionality such as isolation or specialized logic operations without requiring separate dedicated structures, thereby managing complexity through multi-functionality.
Data Source
AI summary
A semiconductor device includes a stacked transistor memory cell. The stacked transistor memory cell includes a bottom tier including a plurality of bottom transistors including at least one non-floating transistor and at least one floating transistor. The at least one floating transistor has at least one terminal being electrically disconnected from other transistors of the stacked transistor memory cell. The stacked transistor memory cell further includes a top tier including a at least one top transistor, and a cross-coupling including epitaxial region (epi) connections and gate to epi connections between the top tier and the bottom tier.