Stacked Transistor Layout for Mixed-Height Standard Cells
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Solution Overview
Problem
The challenge in semiconductor manufacturing is achieving greater cell density and better computing performance within a limited area, particularly when cells with mixed cell heights are involved, leading to layout inefficiencies and area penalties due to white spaces between cells.
Innovation Solution
The integration of multiple active regions and conductive segments in a layered structure, with specific alignments and overlaps, allows for higher cell density and flexibility without inducing white spaces, thereby enhancing computing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If cells with different cell heights are used to improve computing performance, then computing performance is improved, but white spaces are generated between cells leading to reduced cell density
Solution Approach 1:
The patent implements a nested structure where a first cell is positioned within a second cell, and a third cell is positioned within the second cell. This nesting arrangement allows cells of different heights to be integrated without generating white spaces, as the smaller cells are contained within the boundaries of the larger cell, thereby maintaining high cell density while achieving mixed-height configurations for improved computing performance.
Solution Approach 2:
The patent utilizes vertical stacking in the third dimension by positioning cells at different heights (first cell height, second cell height, and third cell height) within the same planar footprint. This dimensional transition from 2D lateral arrangement to 3D vertical arrangement enables mixed-cell-height designs to achieve higher computing performance without sacrificing cell density, as cells are packed more efficiently in the vertical dimension.
2Power
If mixed cell height layout is implemented to improve computing performance, then computing performance is improved, but area penalty occurs due to white spaces
Solution Approach 1:
By nesting the first cell within the second cell and the third cell within the second cell, the patent eliminates the need for additional lateral space that would normally be required for mixed-height cell configurations. The nested arrangement ensures that all cells are contained within the bounding box of the second cell, thereby avoiding area penalties and white spaces that would otherwise occur in conventional mixed-height layouts.
Solution Approach 2:
The patent transitions from 2D lateral cell arrangement to 3D vertical stacking, allowing cells of different heights to be positioned within the same planar area. This dimensional change enables the layout to achieve high computing performance without increasing the overall layout area, as the vertical dimension provides additional space for accommodating mixed-cell-height configurations without lateral expansion.
3Productivity
If cells of different heights are arranged to increase cell density, then cell density is improved, but layout flexibility is reduced due to alignment constraints
Solution Approach 1:
The patent segments the layout into distinct cell units with different heights (first cell, second cell, third cell) that can be independently configured and positioned. This segmentation allows each cell to be optimized for its specific function while maintaining high cell density through the nested arrangement, thereby preserving layout flexibility despite the presence of multiple cell heights.
Solution Approach 2:
By utilizing vertical stacking in the third dimension, the patent decouples the relationship between cell height and lateral position. This dimensional transition allows cells of different heights to be arranged in the vertical direction without imposing strict alignment constraints in the lateral direction, thereby maintaining layout flexibility while achieving high cell density through efficient vertical space utilization.
Data Source
AI summary
An integrated circuit includes a first transistor of a first conductivity type including a first active area extending in a first direction; a second transistor of the first conductivity type including at least two second active areas extending in the first direction and a first gate stripe crossing the at least two second active areas; and a third transistor of a second conductivity type that is stacked on the second transistor and includes at least two third active areas arranged above the at least two second active areas. A top most boundary line of the first active area is aligned with a top most boundary line of one of the at least two third active areas in a layout view.