Stacked Transistor Mo Contacts for Lower SiGe Source-Drain Resistance
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Solution Overview
Problem
Stacked transistor architectures face challenges in reducing extrinsic resistance due to the conductivity of source and drain semiconductor materials and contact resistance, particularly in densely packed vertical structures.
Innovation Solution
Implementing molybdenum (Mo) contact metallization directly with gallium-doped SiGe alloy source and drain semiconductor materials, utilizing epitaxial growth and selective deposition processes to form a silicide interface, thereby reducing contact resistance and extrinsic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If stacked gate-all-around transistor structures with vertical channel stacks are implemented to increase device density, then transistor integration density is improved, but extrinsic resistance increases due to small spaces between vertically stacked channel regions
Solution Approach 1:
The patent applies local quality by creating compositionally graded source and drain regions with varying Ga/Si ratios at different vertical positions and lateral locations. The Ga-enriched regions are specifically positioned at interfaces with contact metallization to reduce contact resistance, while maintaining appropriate composition in channel-contact regions for low barrier height, thereby locally optimizing electrical properties to mitigate extrinsic resistance in the dense stacked architecture
Solution Approach 2:
The patent employs composite materials by integrating multiple semiconductor layers with different compositions (SiGe alloys with varying Ga concentrations) into the source and drain structures. This composite approach combines regions with different electrical characteristics - Ga-enriched regions for low contact resistance and SiGe regions for appropriate band alignment - to simultaneously address both contact resistance and barrier height issues in the high-density stacked transistor configuration
2Reliability
If source and drain semiconductor material conductivity is increased to reduce extrinsic resistance, then contact resistance decreases, but device geometry constraints in densely packed vertical structures limit the effectiveness of this approach
Solution Approach 1:
The patent applies parameter changes by systematically varying the compositional parameters (Ga/Si ratios) of the source and drain materials throughout the vertical stack. By controlling the gradient of Ga concentration as a function of position, the invention optimizes electrical parameters such as carrier concentration and mobility to achieve low contact resistance while adapting to the geometric constraints of the densely packed vertical transistor structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integration of Mo contact metallization with Ga-doped SiGe alloy significantly reduces extrinsic resistance, enhancing the performance of stacked transistors by improving conductivity and reducing contact barriers.
Implementation Method 1
utilizing epitaxial growth and selective deposition processes to form a silicide interface
Implementation Method 2
The integration of Mo contact metallization with Ga-doped SiGe alloy significantly reduces extrinsic resistance, enhancing the performance of stacked transistors by improving conductivity
Data Source
AI summary
Integrated circuitry comprising a ribbon or wire (RoW) transistor stack structure including a plurality of individual source and/or drain material bodies of a p-type conductivity type are directly contacted with molybdenum. In some examples, a source and/or drain material protrusion formed at opposite ends of each of a plurality of channel structures are of a first p-type SiGex composition. Another layer of SiGey, where y is larger than x, is layered over the protrusions. In some further examples, an outer layer of an individual layered SiGe source and/or drain body enriched with Ga (e.g., SiGe: Ga) is directly contacted by molybdenum. In some examples, the SiGe and molybdenum react to form silicide interfacial layer.