Stacked Transistor Neuromorphic Device for CMOS Integration
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Solution Overview
Problem
Current neuromorphic technologies face challenges in integrating large-scale neurons and synapses and implementing learning functions within existing CMOS processes, leading to limitations in processing speed and power consumption, particularly due to the separation of memory and processor functions.
Innovation Solution
A semiconductor device with stacked transistors, including a p-n-i-n nanostructure, that utilizes an existing CMOS process to create a synapse-mimicking and neuron-mimicking device capable of performing logical operations and memorization, with a feedback mechanism allowing retention of previous states even when input signals are removed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional von Neumann architecture is used with separate memory and processor, then existing CMOS process compatibility is maintained, but processing speed is limited due to data access bottlenecks
Solution Approach 1:
The patent merges memory and logic functions into a single device by stacking a first transistor with memory function and a second transistor with logic function vertically. This integration eliminates the need for separate memory and processor components, enabling simultaneous memorization and logical operation within one compact structure, thereby resolving the speed limitation caused by data access bottlenecks while maintaining CMOS compatibility.
Solution Approach 2:
The patent transitions from planar two-dimensional device layout to three-dimensional vertical stacking architecture. By stacking transistors vertically with different conductivity types (n-type and p-type) and different functions (memory and logic) along the vertical dimension, the device achieves higher integration density and functional convergence, overcoming the speed limitations of conventional horizontal architectures.
2Productivity
If neuromorphic technology is used to mimic human neural networks, then parallel processing capability is improved, but integration of large-scale neurons and synapses and implementation of learning functions are limited
Solution Approach 1:
The patent creates a universal neuromorphic device that can perform multiple functions: logical operations through the second transistor, memorization through the first transistor's feedback mechanism, and parallel processing through scalable stacking. This multi-functional design eliminates the need for separate processors for learning operations, enabling large-scale integration of neurons and synapses with built-in learning capabilities within existing CMOS processes.
Solution Approach 2:
The patent implements self-service functionality through the feedback mechanism where the first transistor retains previous state data and automatically provides it to the second transistor for logical operations. This self-contained operation eliminates the need for external processors to control learning operations, enabling autonomous neuromorphic computing with reduced integration complexity.
3Loss of energy
If memory and processor are separated, then functional modularity is maintained, but power consumption increases and integration is limited
Solution Approach 1:
The patent merges memory and logic functions into a single vertically-stacked device, eliminating the need for data transfer between separate memory and processor components. This integration reduces power consumption by removing redundant data access operations while simultaneously improving integration density, as the stacked structure allows multiple functions to coexist in a compact footprint compatible with existing CMOS processes.
Data Source
AI summary
A semiconductor device includes stacked transistors. Each of the transistors includes a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region. A gate electrode is disposed to cover the intrinsic region, and a gate insulating layer is disposed between the gate electrode and the intrinsic region.