Stacked III-V and Si Transistors for Parasitic Reduction
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Solution Overview
Problem
Conventional packaging techniques for combining III-Nitride transistors with silicon FETs increase parasitic inductance, resistance, thermal dissipation requirements, and manufacturing costs, negating the benefits of III-Nitride devices in high-power applications.
Innovation Solution
A stacked composite device configuration where a group III-V transistor is stacked over a group IV lateral transistor, utilizing a larger group IV active die as the bottom layer and a smaller group III-V active die on top, reducing parasitic inductance and resistance while enhancing thermal dissipation and reducing form factor and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging techniques are used to combine III-Nitride transistors with silicon FETs, then the devices can be packaged together, but parasitic inductance and resistance increase
Solution Approach 1:
The patent merges the III-Nitride transistor and silicon FET into a single integrated package structure, placing both devices on the same substrate with shared terminal connections. This combining approach reduces the number of external connections and inter-package parasitics, directly addressing the harmful effect of parasitic inductance and resistance while maintaining reliable device operation
Solution Approach 2:
The patent implements a nested configuration where the III-Nitride transistor and silicon FET are arranged in a cascode topology with the source of the III-Nitride device nested within the drain region of the silicon FET. This nesting eliminates the need for external connection between the devices, reducing parasitic inductance and resistance in the current path
2Reliability
If conventional packaging techniques are used to combine III-Nitride transistors with silicon FETs, then the devices can be packaged together, but thermal dissipation requirements increase
Solution Approach 1:
The patent merges the thermal management of both devices by providing a shared heat sink structure that contacts both the III-Nitride transistor and silicon FET. This combined thermal path consolidates heat dissipation resources, reducing the overall thermal dissipation requirements compared to separate packaging approaches
Solution Approach 2:
The patent implements nested thermal management where the heat sink structure is positioned to simultaneously contact both devices, with the III-Nitride transistor's heat sink potentially nested within or adjacent to the silicon FET's heat sink structure, creating an integrated thermal management system
3Reliability
If conventional packaging techniques are used to combine III-Nitride transistors with silicon FETs, then the devices can be packaged together, but package form factor increases
Solution Approach 1:
The patent merges both devices into a single compact package footprint by placing the III-Nitride transistor and silicon FET on the same substrate with shared terminal connections. This integration eliminates the need for separate packages and external interconnections, directly reducing the overall package form factor while maintaining reliable device integration
Solution Approach 2:
The patent implements a nested spatial arrangement where the III-Nitride transistor is positioned within the footprint of the silicon FET package area, with the source region of the III-Nitride device nested within the drain region of the silicon FET. This nested configuration maximizes space utilization and minimizes the overall package form factor
4Reliability
If conventional packaging techniques are used to combine III-Nitride transistors with silicon FETs, then the devices can be packaged together, but manufacturing costs increase
Solution Approach 1:
The patent merges the manufacturing process by providing a unified package structure with shared terminal connections and integrated heat sink, eliminating the need for separate packaging operations and external interconnections. This consolidation reduces manufacturing steps and associated costs while maintaining reliable device combination
Solution Approach 2:
The patent implements a nested device configuration that simplifies the manufacturing process by reducing the number of assembly steps required. The nested arrangement allows for more straightforward integration and testing, reducing manufacturing complexity and cost compared to conventional side-by-side packaging techniques
Data Source
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AI summary
In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device.