3D Stacked Transistor Power-Line Layout for Dense IC Routing
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Solution Overview
Problem
As integrated circuits become smaller, there is a need to reduce the overall area occupied by the circuit elements and the distance between them, while maintaining efficient power distribution and routing flexibility.
Innovation Solution
The integration of a first and second transistor with gate structures wrapping around the active regions, where the first power line is above the first transistor and the second power line is below the second transistor, with the second power line having a larger area than the first, allowing for improved routing flexibility and increased density by sharing the same power line for both transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the area of integrated circuit elements is decreased to reduce overall layout area, then the density increases, but the routing flexibility and power distribution efficiency deteriorate
Solution Approach 1:
The patent transitions from planar power line arrangement to three-dimensional stacking, where power lines are positioned at different vertical levels (first power line above first transistor, second power line below second transistor). This vertical dimensionality allows power distribution without increasing lateral footprint, thereby maintaining routing flexibility while reducing layout area.
Solution Approach 2:
The larger area second power line serves multiple functions: it provides power to the second transistor directly below it, and also serves as a shared power line for both transistors through vertical coupling. This multi-functionality reduces the total number of power lines needed, improving power distribution efficiency while maintaining adaptability.
2Area of moving object
If the distance between circuit elements is reduced to increase density, then the layout area decreases, but the power grid distribution efficiency deteriorates
Solution Approach 1:
By positioning power lines at different vertical levels rather than horizontally adjacent, the patent enables effective power distribution to closely spaced transistors without requiring large lateral distances. The vertical separation maintains electrical isolation while the larger area second power line ensures sufficient current capacity.
Solution Approach 2:
The patent combines power distribution functions by allowing the second power line to serve both the second transistor and the first transistor. This merging of functions reduces the total power grid infrastructure needed, improving power distribution efficiency while supporting reduced element spacing.
3Adaptability or versatility
If transistors are arranged with separate power lines to maintain power distribution efficiency, then the routing flexibility is improved, but the device complexity and area increase
Solution Approach 1:
The second power line is designed with larger area to perform multiple functions: it directly powers the second transistor and simultaneously serves as a shared power line for the first transistor through vertical coupling. This multi-functionality reduces the total number of power lines required, simplifying the overall device structure while maintaining routing flexibility.
Data Source
AI summary
A method, comprising forming an integrated circuit over a first power line, wherein the integrated circuit comprises a first transistor having a first active region and a first gate structure in contact with the first active region, wherein the first active region has first source/drain regions; a second transistor over the first transistor, and having a second active region and a second gate structure in contact with the second active region, wherein the second active region has second source/drain regions, wherein the first power line is electrically connected to one of the first source/drain regions of the first active region of the second transistor; and a second power line over the second transistor, wherein the second power line is electrically connected to one of the second source/drain regions of second active region of the second transistor.