Stacked Transistor PUF Layout for Low-Leakage Unique IDs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current physically unclonable function (PUF) circuits, particularly those based on static random-access memory (SRAM) cells, face challenges in providing unique identifiers with minimal area usage and low current leakage.
Innovation Solution
The implementation of a PUF circuit using stacked transistor devices, where each device pair consists of first and second transistors coupled in series between bit lines and a power distribution node, with gates connected to word lines, allowing for unique identifier outputs based on physical differences and reduced current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SRAM-based PUF circuits are used, then unique identifiers can be generated, but the area consumption is large and current leakage is high
Solution Approach 1:
The patent changes the fundamental circuit topology from SRAM-based to stacked transistor-based PUF. This parameter change in circuit architecture enables unique identifier generation with significantly reduced area consumption and lower current leakage, directly resolving the technical contradiction between reliability of unique ID generation and area efficiency
2Reliability
If SRAM-based PUF circuits are used, then unique identifiers can be generated, but current leakage is high
Solution Approach 1:
The patent changes the fundamental circuit topology from SRAM-based to stacked transistor-based PUF. This parameter change in circuit architecture enables unique identifier generation with significantly reduced area consumption and lower current leakage, directly resolving the technical contradiction between reliability of unique ID generation and area efficiency
3Area of moving object
If transistor density is increased through process technology developments, then component sizes are reduced, but spacing is tightened making PUF implementation more difficult
Solution Approach 1:
The patent employs stacked transistor structures that utilize the vertical dimension (third dimension) by stacking transistors on top of each other rather than placing them side-by-side in the planar domain. This dimensional transition allows dense integration while maintaining sufficient spacing between PUF devices, resolving the contradiction between miniaturization and manufacturability
Data Source
AI summary
An IC device includes a first and second stacked transistor structures including respective first and second and third and fourth transistors in a semiconductor substrate, first and second bit lines and a word line on one of a front or back side of the semiconductor substrate, and a power supply line on the other of the front or back side. The first transistor includes a source/drain (S/D) terminal electrically connected to the first bit line, a S/D terminal electrically connected to a S/D terminal of the second transistor, and a gate electrically connected to the word line, the third transistor includes a S/D terminal electrically connected to the second bit line, a S/D terminal electrically connected to a S/D terminal of the fourth transistor, and a gate electrically connected to the word line, and the second and fourth transistors include S/D terminals electrically connected to the power supply line.