Stacked Transistor Resistor Structure for Process-Compatible Resistance Tuning
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Solution Overview
Problem
Existing integrated circuit devices face challenges in forming resistor structures that can be manufactured using processes compatible with stacked transistors, while also achieving various resistance values.
Innovation Solution
The proposed solution involves forming resistor structures with a substrate, an upper semiconductor layer, a lower semiconductor layer, and first and second resistor contacts. These layers and contacts are configured such that at least one of the upper semiconductor layer, the lower semiconductor layer, and a portion of the substrate contacts the resistor contacts, allowing for the formation of resistor structures that can be integrated with stacked transistors without additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If resistor structures are formed using separate manufacturing processes, then various resistance values can be achieved, but the manufacturing complexity and process compatibility with stacked transistors deteriorates
Solution Approach 1:
The patent applies universality by designing a resistor structure that uses the same semiconductor layers (upper semiconductor layer 26U_1, lower semiconductor layer 26L1) and manufacturing processes as the stacked transistors. The resistor elements are formed from the same epitaxial growth processes that create the transistor source/drain regions, allowing the structure to serve dual purposes: as active transistor components and as resistive elements for bias circuits and feedback paths.
Solution Approach 2:
The patent merges the resistor formation process with the stacked transistor manufacturing process. The resistor elements are created by selectively doping or configuring portions of the semiconductor layers that are already being formed for the transistors. This combining eliminates separate resistor fabrication steps and achieves process compatibility while maintaining the ability to produce various resistance values through different doping configurations.
2Area of moving object
If stacked transistor structures are introduced to reduce area, then integration density improves, but the ability to form compatible resistor structures deteriorates
Solution Approach 1:
The semiconductor layers (upper semiconductor layer 26U1, lower semiconductor layer 26L1) are designed to serve multiple functions: they form the active regions of the stacked transistors and simultaneously serve as the resistive elements for integrated resistors. This multi-functionality allows the compact stacked transistor structure to coexist with resistor structures without requiring additional processing steps or sacrificing manufacturing compatibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process by using common processes for forming both resistor structures and stacked transistors, enabling the creation of resistor structures with various resistance values while maintaining integration density.
Implementation Method 1
forming a lower semiconductor layer by performing a first epitaxial growth process using the lower thin semiconductor layer as a first seed layer, forming an upper semiconductor layer by performing a second epitaxial growth process using the upper thin semiconductor layer as a second seed layer
Data Source
AI summary
Resistor structures of stacked devices and methods of forming the same are provided. The, resistor structures may include a substrate, an upper semiconductor layer that may be spaced apart from the substrate in a vertical direction, a lower semiconductor layer that may be between the substrate and the upper semiconductor layer, and first and second resistor contacts that may be spaced apart from each other in a horizontal direction. At least one of the upper semiconductor layer, the lower semiconductor layer, and a portion of the substrate may contact the first and second resistor contacts.