Stacked Transistor Semiconductor Device for High Integration Density
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration density, high on-state current, and reliable electrical characteristics while maintaining high productivity in fabrication.
Innovation Solution
A semiconductor device comprising a first transistor, a second transistor, and an insulating layer, where the transistors include specific conductive and semiconductor layers with gate insulating layers, and the insulating layer is in contact with the transistors to facilitate high-density transistor arrangement and efficient current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are miniaturized to increase integration density, then the degree of integration is improved, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional stacked transistor configurations, where multiple transistors are vertically integrated above a common substrate. This vertical stacking enables higher integration density without proportionally increasing manufacturing complexity, as the same fabrication processes can be applied across multiple layers.
Solution Approach 2:
The patent divides the semiconductor structure into distinct functional layers including substrate, buffer layer, active layer, and contact layers. Each layer is independently fabricated and optimized, allowing precise control over material properties and interfaces while maintaining overall integration density.
2Quantity of substance
If transistors are miniaturized to increase integration density, then the degree of integration is improved, but on-state current decreases
Solution Approach 1:
The patent applies different material compositions and structural configurations to specific regions of the transistor. The active layer uses optimized semiconductor materials with high carrier mobility, while contact layers use highly conductive materials. This localized optimization maintains high on-state current despite miniaturization.
Solution Approach 2:
The patent employs composite material structures combining different semiconductor compounds and conductive materials in layered configurations. These composite structures provide both the miniaturization needed for high integration and the electrical properties needed for high on-state current through synergistic material combinations.
3Quantity of substance
If complex multi-layer transistor structures are implemented to achieve high integration, then device complexity increases, but productivity decreases
Solution Approach 1:
The patent designs the multi-layer structure so that single fabrication processes serve multiple functions across different layers. For example, ion implantation and annealing processes simultaneously activate dopants, repair damage, and form contacts in multiple layers without requiring separate processing steps for each layer.
Solution Approach 2:
The patent performs preliminary fabrication steps such as forming buffer layers and preparing substrate surfaces before main transistor fabrication. These preliminary actions pre-condition the structure to receive subsequent layers and processes, reducing overall fabrication complexity and improving productivity.
Data Source
AI summary
A semiconductor device having a high degree of integration is provided. The semiconductor device includes a first and a second transistor, and an insulating layer. The first transistor includes a source electrode, a drain electrode over the insulating layer over the source electrode, a first semiconductor layer in contact with a top surface of the source electrode, an inner wall of an opening provided in the insulating layer, and a top surface of the drain electrode, a first gate insulating layer in contact with a top surface and a side surface of the first semiconductor layer, and a first gate electrode over the first gate insulating layer that includes a region overlapping with the inner wall of the opening. The second transistor includes a second semiconductor layer over the insulating layer, the source electrode in contact with one of a top surface and a side surface of the second semiconductor layer, the drain electrode in contact with the other of the top surface and the side surface of the second semiconductor layer, a second gate insulating layer in contact with the top surface of the second semiconductor layer, a top surface and a side surface of the source electrode, and a top surface and a side surface of the drain electrode, and a second gate electrode over the second gate insulating layer. The first semiconductor layer is in contact with the second gate electrode.