Stacked Semiconductor Transistor Structure With Shared Gate Control
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Solution Overview
Problem
The demand for increased integration, reliability, and multifunctionality in semiconductor devices has not been adequately met by existing technologies, which face challenges in enhancing semiconductor device performance while maintaining manufacturing costs and miniaturization.
Innovation Solution
The semiconductor device design includes a substrate with a device isolation film, active regions, channel regions, gate structures, source/drain regions, and a shared gate electrode configuration, allowing for improved integration by using a cover semiconductor layer electrically separated from the active region to create additional channel regions and source/drain regions, enabling enhanced transistor operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing semiconductor device structures are used, then manufacturing processes are simpler, but integration and performance enhancement are limited
Solution Approach 1:
The patent implements a three-dimensional stacked transistor structure where a cover semiconductor layer is formed above the substrate, creating vertical channel regions that extend in the thickness direction. This dimensional transition from planar to vertical architecture enables higher integration density without proportionally increasing lateral device footprint, directly resolving the contradiction between integration enhancement and structural complexity.
Solution Approach 2:
The cover semiconductor layer is nested above the substrate, with the gate structure enveloping the channel regions from multiple sides. The gate electrode wraps around the channel in a U-shape configuration, creating a nested arrangement where the gate controls the channel from three dimensions. This nesting approach maximizes control efficiency and integration within a compact vertical space.
2Area of moving object
If miniaturization is pursued, then device density increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
By transitioning to vertical channel regions extending in the thickness direction, the patent reduces the lateral footprint of transistors while maintaining effective channel control length. The gate structure's three-dimensional wrapping configuration ensures precise electrical control of the channel without requiring proportionally tighter lateral fabrication tolerances, thus enabling miniaturization without linearly increasing manufacturing precision demands.
3Reliability
If performance enhancement is achieved through structure optimization, then device speed and reliability improve, but manufacturing complexity increases
Solution Approach 1:
The shared gate structure serves multiple functions simultaneously: it controls both the first channel region in the substrate and the second channel region in the cover semiconductor layer, enabling independent transistor operation while using a single gate electrode. This multi-functional design enhances device reliability and performance through improved channel control without proportionally increasing manufacturing complexity, as the gate formation process remains unified rather than requiring separate gates for each channel.
Data Source
AI summary
A semiconductor device includes a substrate having an active region defined by a device isolation film and providing a first channel region; a first source/drain region in the active region on first and second sides of the first channel region; a gate structure having a first gate insulating film, a shared gate electrode, and a second gate insulating film, sequentially arranged on the active region; a cover semiconductor layer on the second gate insulating film and electrically separated from the active region to provide a second channel region; a second source/drain region in the cover semiconductor layer on first and second sides of the second channel region; first and second source/drain contacts respectively connected to the first and second source/drain regions; and a shared gate contact connected to the shared gate electrode.