Stacked Transistor Backside Reveal for Shared Gate Patterning
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Solution Overview
Problem
Conventional techniques for manufacturing stacked transistors are costly and time-consuming due to the need for separate lithographical and processing operations for each transistor, making it difficult to scale down semiconductor devices to submicron dimensions while maintaining high integration levels.
Innovation Solution
The backside reveal process is used to fabricate stacked devices, where an interconnect layer is deposited on a first device layer on a second device layer, and the second device layer is revealed from the substrate side, allowing for the formation of gate and source/drain regions from the backside, simplifying the manufacturing process and reducing costs by sharing fin and gate patterning operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate lithographical and processing operations are performed for each transistor in stacked structures, then manufacturing precision can be maintained, but manufacturing cost and time increase significantly
Solution Approach 1:
The patent merges the fabrication of multiple stacked transistors into a single unified process. A common gate structure is formed that simultaneously defines multiple transistors stacked vertically, eliminating the need for separate lithography steps for each transistor. The gate is formed as a single continuous structure that patterns all transistors in the stack concurrently, thereby reducing manufacturing cost and complexity while maintaining precision through the unified approach.
Solution Approach 2:
The gate structure serves multiple functions simultaneously: it acts as the control electrode for multiple stacked transistors, provides a common reference plane for alignment, and enables concurrent patterning of all transistors in the stack. This multi-functional gate design eliminates the need for separate processing operations for each transistor layer, directly addressing the contradiction between precision and manufacturing ease.
2Ease of manufacture
If conventional frontside techniques are used to fabricate lower device layer, then manufacturing process is simpler, but gate and source/drain regions of lower device layer cannot be formed
Solution Approach 1:
The patent inverts the conventional fabrication sequence by forming the gate structure first from the frontside, then using this gate as a template to define source/drain regions in the lower device layer. Instead of attempting to form source/drain regions before the gate (which is impossible with frontside techniques), the method uses the gate's position to subsequently define where source/drain regions should be formed, enabling complete transistor fabrication including the lower device layer.
Solution Approach 2:
The gate structure is formed in advance as a preliminary step before forming source/drain regions. This preliminary gate formation establishes the spatial reference and patterning template that guides subsequent source/drain region fabrication. By performing the gate formation first, the method enables the lower device layer's gate and source/drain regions to be properly formed, overcoming the limitations of conventional frontside techniques.
3Productivity
If device dimensions are scaled down to submicron levels, then device integration density increases, but fabrication difficulty increases due to physics challenges at small dimensions
Solution Approach 1:
The patent combines multiple transistor fabrication operations into a single unified process that forms stacked transistors simultaneously. By merging the patterning and formation steps for multiple transistors into one concurrent operation, the method achieves high integration density while avoiding the cumulative complexity and alignment challenges that would arise from performing separate submicron fabrication steps for each individual transistor.
Data Source
AI summary
A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.