Stacked Multi-Bridge Transistor Structure for Short-Channel Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration and performance due to limitations in scaling and short channel effects, particularly in multi-gate transistors with stacked structures.
Innovation Solution
The semiconductor device incorporates a substrate with stacked active patterns and gate structures, along with epitaxial and via structures that enhance connectivity and channel regions, allowing for improved integration and performance through a multi-bridge channel configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a multi-gate transistor with stacked structure is used to increase integration density, then the degree of integration is improved, but the manufacturing complexity increases
Solution Approach 1:
The device is divided into distinct stacked regions with upper and lower active patterns separated by intermediate insulating patterns. This segmentation allows independent formation and optimization of each transistor layer, simplifying the manufacturing process while maintaining high integration density.
Solution Approach 2:
The patent transitions from planar transistor arrangements to a three-dimensional stacked configuration where transistors are arranged vertically along the first direction. This dimensional change enables higher integration density by utilizing the vertical space above the substrate more effectively.
2Area of moving object
If the gate length is not increased, then the device area is reduced, but the current control capability deteriorates
Solution Approach 1:
The patent employs a three-dimensional channel structure where the channel extends in multiple directions (first, second, and third directions) rather than a simple planar configuration. This multi-dimensional channel provides enhanced gate control over the current flow without requiring an increase in gate length, thus maintaining compact device area while improving current control capability.
3Reliability
If a stacked multi-gate transistor structure is implemented, then the short channel effect is suppressed, but the device complexity increases
Solution Approach 1:
The stacked transistor structure divides the channel into separate upper and lower regions with distinct active patterns and epitaxial structures. This segmentation allows each region to be independently optimized for suppressing short channel effects while maintaining manageable structural complexity through modular design.
Solution Approach 2:
Different regions of the stacked structure have locally optimized properties - the upper active pattern and lower active pattern have different geometries and epitaxial configurations tailored to their specific positions. This local quality optimization enhances short channel effect suppression in each region while keeping the overall structure complexity controlled through systematic variation rather than complete redesign.
Data Source
AI summary
A semiconductor device includes a first lower epitaxial pattern on a side of a gate structure, wherein the first lower epitaxial pattern is connected to a lower active pattern; a first upper epitaxial pattern on another side of the gate structure, wherein the first upper epitaxial pattern is connected to an upper active pattern; a cut pattern that is spaced apart from the lower and upper active patterns, is adjacent the gate structure, and extends in a first direction; and a via structure connected to the first lower epitaxial pattern and the first upper epitaxial pattern in the cut pattern, wherein the via structure includes a first pillar part overlapping the first upper epitaxial pattern in a second direction, a second pillar part overlapping the first lower epitaxial pattern in the second direction, and a connecting part extending in the first direction to connect the first and second pillar parts.