Stacked Semiconductor Transistor Structure for Short-Channel Reliability
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving transistors with minute sizes, short channel lengths, high on-state currents, reliable electrical characteristics, and reduced area occupation, while maintaining high productivity and low power consumption.
Innovation Solution
A semiconductor device structure is designed with specific conductive and insulating layers, including angled openings and varying thicknesses of insulating and semiconductor layers to optimize transistor dimensions and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the transistor size is reduced to achieve high-definition display, then the pixel size can be reduced and definition increased, but the manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The patent transitions from planar transistor configuration to a three-dimensional stacked structure with multiple conductive layers (first conductive layer 102, second conductive layer 104) separated by insulating layers. This vertical stacking enables miniaturization while maintaining manufacturing precision through standardized layer thicknesses and alignment features.
Solution Approach 2:
The patent implements a nested structure where the first semiconductor layer 106 is positioned within openings of the first insulating layer 108, which itself is sandwiched between conductive layers. This nested arrangement maximizes space utilization and maintains precise geometric relationships essential for manufacturing.
2Length of moving object
If the channel length is shortened to reduce transistor area, then the device size is reduced, but the on-state current and electrical characteristics deteriorate
Solution Approach 1:
The patent compensates for short channel length by introducing vertical stacking dimensions. The first and second conductive layers 102, 104 are positioned at different vertical levels with the semiconductor layer 106 connecting them, creating a three-dimensional current path that maintains electrical performance despite reduced planar dimensions.
Solution Approach 2:
The patent employs a composite structure combining multiple materials with different properties: conductive layers (metal or doped semiconductor), insulating layers (dielectric materials), and semiconductor layers. This composite approach allows optimization of each layer's thickness and material properties to maintain electrical characteristics while minimizing overall device size.
3Adaptability or versatility
If multiple transistors are integrated to increase functionality, then the device performance is improved, but the total area occupied increases
Solution Approach 1:
The patent utilizes vertical stacking to integrate multiple functional elements within a compact footprint. The first and second conductive layers 102, 104 with their respective openings create stacked transistor structures that occupy minimal planar area while providing multiple functional pathways vertically.
Solution Approach 2:
The patent designs a universal stacked transistor structure that can serve multiple functions: the first conductive layer 102 and second conductive layer 104 can function as different electrodes (source, drain, gate), and the same basic structure can be replicated and combined to form complex circuits, achieving multi-functionality through modular design.
4Area of moving object
If the insulating layer thickness is reduced to minimize device area, then the area is reduced, but the electrical isolation and reliability are compromised
Solution Approach 1:
The patent compensates for reduced insulating layer thickness by utilizing vertical stacking geometry. The first insulating layer 108 is positioned between conductive layers at different vertical levels, and the angled side surfaces create effective electrical isolation paths that are longer than the direct vertical thickness, maintaining isolation reliability while minimizing area.
Solution Approach 2:
The patent implements nested openings where the first opening 110 in the first insulating layer 108 and the second opening 112 in the second conductive layer 104 are positioned to overlap or align. This nesting creates multi-level electrical isolation zones that provide redundant isolation paths, ensuring reliability even with thin insulating layers.
Data Source
AI summary
A semiconductor device that has both low power consumption and high performance is provided. The semiconductor device includes a first conductive layer, a second conductive layer, a first semiconductor layer, a second insulating layer over the first semiconductor layer, a third conductive layer over the second insulating layer, and a first insulating layer sandwiched between the first conductive layer and the second conductive layer. The first insulating layer includes a first opening reaching the first conductive layer. The second conductive layer includes a second opening. The first opening and the second opening overlap with each other in a plan view. In the first opening, the first semiconductor layer is in contact with the top surface of the first conductive layer and the side surface of the first insulating layer. In the second opening, the first semiconductor layer is in contact with the side surface of the second conductive layer. The first semiconductor layer includes a region overlapping with the third conductive layer with the second insulating layer therebetween. The side surface of the first insulating layer in the first opening includes a region forming an angle of greater than or equal to 10° and less than 55° with the top surface of the first conductive layer.