Stacked Transistor Metallization Structure for Sidewall Interconnects
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Solution Overview
Problem
The challenge in modern electronics is connecting physically separated upper and lower levels of transistors in high-density transistor arrays, where scaling reduces the effective distance between transistors, making it difficult to efficiently route connections to multiple metallization structures in lower level transistors without occupying significant lateral real estate.
Innovation Solution
The implementation of an epitaxial structure that induces strain in upper level transistors, allowing the upper metallization structure to couple with the metallization of lower level transistors, featuring portions that extend under the gate, laterally beyond the spacer, and below the fin structure, coupled with a metallization structure that reduces effective contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional metallization structures are used to connect stacked transistors, then connectivity between levels is achieved, but lateral footprint increases significantly
Solution Approach 1:
The patent transitions from planar metallization to three-dimensional sidewall metallization structures. Metallization is formed on the sidewalls of epitaxial structures, allowing vertical stacking connections without requiring additional lateral space. This dimensional change enables inter-level connectivity while maintaining compact footprint.
Solution Approach 2:
The metallization structures are nested within and around the epitaxial structures. The conformal metallization layers wrap around the semiconductor fins, utilizing the vertical space already defined by the transistor structure. This nesting approach allows multiple metallization layers to be integrated without increasing lateral dimensions.
2Productivity
If transistor size is scaled down to increase density, then transistor density improves, but space for metallization structures between stacked transistors is reduced
Solution Approach 1:
By moving metallization from horizontal routing to vertical sidewall positioning, the invention decouples metallization space requirements from lateral transistor pitch. This allows continued transistor scaling while maintaining adequate metallization formation space through vertical epitaxial growth and sidewall deposition.
Solution Approach 2:
The invention changes the geometric parameters of metallization formation by using conformal deposition on vertical sidewalls rather than planar surfaces. This parameter change in deposition geometry allows metallization to be formed in the vertical dimension, preserving lateral space for higher transistor density.
3Reliability
If epitaxial structure extends under gate and beyond spacer, then strain induction and connectivity are improved, but manufacturing complexity increases
Solution Approach 1:
The epitaxial structure is formed with extended regions under the gate and beyond the spacer during the initial epitaxial growth process, before subsequent processing steps. This preliminary formation of the extended epitaxial structure simplifies later metallization deposition and patterning by providing pre-defined sidewall surfaces for conformal coating.
Solution Approach 2:
The extended epitaxial structure serves multiple functions simultaneously: it provides strain induction for transistor performance, creates sidewall surfaces for metallization formation, and enables connectivity between stacked levels. This multi-functionality reduces the need for separate structures, thereby managing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient connectivity between transistors by reducing contact resistance and optimizing strain, thereby improving processing efficiency and transistor density without increasing footprint.
Implementation Method 1
an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator, wherein the epitaxial structure includes a semiconductor material different from the semiconductor material of the fin structure and an impurity dopant
Data Source
AI summary
A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.