Monolithic Stacked Transistor Layout With Split Upper Fin Channels
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Solution Overview
Problem
Existing methods for forming stacked transistor devices, such as CFET devices, are limited to forming bottom and top devices with the same channel geometry, which may not optimize device performance.
Innovation Solution
A method is developed to form a stacked transistor device comprising a lower nanosheet field-effect transistor (NSHFET) structure and an upper fin field-effect transistor (FinFET) structure by embedding a fin structure in a process layer, removing the capping layer to expose the upper surface, forming spacer layers, etching back to create a reduced-width gap, and splitting the upper channel layer into two fins, followed by forming a gate structure and source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing monolithic processes are used to form stacked transistor devices, then the bottom and top devices can be formed simultaneously, but both devices are constrained to have the same channel geometry which limits device performance optimization
Solution Approach 1:
The patent divides the channel formation process into separate segments: the bottom device channel is formed first, then the top device channel is formed subsequently with different geometry. This segmentation allows each device to have optimized channel dimensions independent of the other, resolving the contradiction between simultaneous formation and geometry flexibility.
Solution Approach 2:
The bottom device channel is formed in advance before the top device channel. This preliminary action enables the bottom channel to be established with its optimal geometry first, then the top channel can be formed with different geometry requirements, allowing both devices to be formed simultaneously in the final structure while maintaining geometry flexibility.
2Reliability
If different channel geometries are implemented for bottom and top devices, then device performance can be optimized, but the process complexity increases
Solution Approach 1:
The patent applies local quality by forming the bottom device channel and top device channel with different geometries tailored to their specific performance requirements. The bottom channel uses one geometry optimized for its function, while the top channel uses a different geometry optimized for its function, allowing each region to have the quality needed for its specific purpose.
Solution Approach 2:
The patent resolves process complexity by transitioning to vertical stacking in the third dimension rather than lateral arrangement. By forming channels with different geometries in the vertical stack, the patent achieves performance optimization without requiring complex lateral process variations, as the dimensional transition simplifies the overall fabrication approach.
3Ease of manufacture
If uniform channel geometry is used for both devices, then the fabrication process is simpler, but device performance optimization is limited
Solution Approach 1:
The fabrication process is segmented into distinct stages: bottom channel formation, intermediate processing, and top channel formation. This segmentation maintains relative process simplicity at each stage while enabling different channel geometries, thus preserving ease of manufacture while achieving performance optimization.
Solution Approach 2:
The bottom channel is formed as a preliminary structure before top channel formation. This preliminary action establishes a foundation that simplifies subsequent processing, as the bottom channel structure serves as a reference and support for the top channel formation, maintaining fabrication simplicity while enabling geometry differentiation.
Data Source
AI summary
The present disclosure relates to a method for forming a stacked transistor device comprising a lower NSHFET structure and an upper FinFET structure including: forming a fin structure comprising: a lower device sub-stack comprising a number of lower channel nanosheets, a middle insulating layer, an upper device sub-stack comprising an upper channel layer, and a capping layer; forming a process layer embedding the fin structure; subsequent to forming the process layer, removing the capping layer from the fin structure to define a gap exposing the upper device sub-stack; forming spacer layers on opposite side surfaces of the gap to form a reduced-width gap; splitting the upper channel layer by etching back an upper surface thereof via the reduced-width gap to form two upper channel fins; subsequent to forming the upper channel fins, removing the spacer layers; and thereafter: forming a gate structure; and forming source and drain regions for the lower channel nanosheets and the upper channel fins.