Stacked Transistor Threshold Tuning With Dipole Gate Insulators
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Solution Overview
Problem
Conventional methods face challenges in forming lower transistors with different threshold voltages in stacked integrated circuit devices, as the overlap of upper transistors complicates the formation of distinct lower transistors, often requiring multiple patterning processes and high-temperature annealing that can damage existing transistors.
Innovation Solution
The solution involves forming gate insulators with different dipole elements or areal densities to achieve varying threshold voltages for lower transistors without the need for multiple patterning processes, while upper transistors are formed with distinct gate work function layers, allowing for the omission of high-temperature annealing and maintaining uniform lower gate work function layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form lower transistors with different threshold voltages in stacked devices, then multiple patterning processes and high-temperature annealing are required, but this damages existing transistors and increases process complexity
Solution Approach 1:
The patent applies local quality by forming gate insulators with different dipole element compositions or areal densities in specific regions to achieve different threshold voltages for lower transistors. This allows each lower transistor to have customized threshold voltage characteristics without requiring multiple patterning processes, thereby reducing process complexity while maintaining manufacturing precision.
Solution Approach 2:
The patent changes the physical parameters of the gate insulator by varying the dipole element composition or areal density to directly control the threshold voltage of lower transistors. This parameter change approach eliminates the need for high-temperature annealing and multiple patterning, thus avoiding damage to existing transistors and simplifying the overall manufacturing process.
2Manufacturing precision
If multiple patterning processes are used to form lower transistors with different threshold voltages, then threshold voltage differentiation is achieved, but the manufacturing process becomes more complex and time-consuming
Solution Approach 1:
The patent implements preliminary action by pre-forming gate insulators with different dipole element compositions or areal densities before transistor fabrication. This preliminary differentiation of threshold voltages through gate insulator design eliminates the need for subsequent multiple patterning processes, significantly reducing manufacturing time while maintaining precise threshold voltage control.
3Manufacturing precision
If high-temperature annealing is applied to form lower transistors, then threshold voltage adjustment is possible, but existing transistors are damaged
Solution Approach 1:
The patent substitutes the thermal field (high-temperature annealing) with an electric field approach by designing gate insulators with different dipole element compositions or areal densities. This substitution allows precise threshold voltage control through material composition rather than thermal processing, thereby maintaining transistor integrity and reliability while achieving the desired threshold voltage differentiation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of lower transistors with different threshold voltages without damaging existing transistors during high-temperature processes, simplifying the manufacturing process and improving the integration of stacked transistors in integrated circuit devices.
Implementation Method 1
a first lower gate insulator that includes first dipole elements; a second lower gate insulator that includes second dipole elements
Data Source
AI summary
Integrated circuit devices may include two transistor stacks including lower transistors having different threshold voltages and upper transistors having different threshold voltages. Gate insulators of the lower transistors may have different dipole elements or different areal densities of dipole elements, and the upper transistors may have different gate electrode structures.