Stacked Transistor Source/Drain Interconnects Using Vertical Epitaxy
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Solution Overview
Problem
Existing 3D integrated circuit technologies face challenges in forming efficient interconnects between source/drain regions of stacked transistors, often requiring significant additional space and relying on complex routing methods.
Innovation Solution
The use of highly doped epitaxial material or metal interconnects that seed from the upper transistor's channel region or adjacent semiconductor material, extending downward to contact the lower transistor's source/drain region, allowing for efficient vertical interconnects without additional space, and optionally trimming the epitaxial material to create a recess filled with metal for improved conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional routing methods are used to form interconnects between source/drain regions of stacked transistors, then electrical connection is achieved, but significant additional space is required
Solution Approach 1:
The patent transitions from lateral routing in the X-Y plane to vertical routing in the Z-dimension. The interconnect structure extends downward from the upper transistor's source/drain region through the isolation layer to contact the lower transistor's source/drain region, utilizing the vertical dimension to achieve electrical connection without requiring additional lateral space.
Solution Approach 2:
The interconnect structure is nested within the existing source/drain region footprint. The vertical interconnect is formed by extending conductive material downward from the upper transistor's source/drain region, effectively nesting the interconnect function within the already allocated space of the source/drain region rather than requiring separate routing space.
2Reliability
If complex routing methods are used to connect stacked transistors, then electrical connection is established, but the interconnect process becomes complex
Solution Approach 1:
The patent merges the source/drain region formation with the interconnect formation into a single integrated process. The same epitaxial growth process that creates the source/drain region in the upper transistor also creates the vertical interconnect extending to the lower transistor, eliminating the need for separate, complex routing steps.
Solution Approach 2:
The epitaxial growth process serves multiple functions simultaneously: it forms the source/drain region of the upper transistor, creates the vertical interconnect structure, and establishes electrical contact with the lower transistor's source/drain region. This multi-functionality simplifies the overall manufacturing process by reducing the number of discrete steps required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables low-resistivity contacts between stacked devices, reducing the need for additional space and simplifying the interconnect process, while maintaining high conductivity and flexibility in material composition and configuration.
Implementation Method 1
The interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed vertical portion of the upper transistor's channel region (or a remaining stub or portion of semiconductor material adjacent the channel region, as will be discussed in turn) and extends downward into a recess that exposes the lower transistor's source/drain contact structure.
Data Source
AI summary
Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor's source/drain contact structure.