3D Stacked Transistor Wiring Layout With Shared Vertical Gates
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Solution Overview
Problem
The challenge in semiconductor technology is to enhance circuit wireability in three-dimensional stacked transistor structures, as traditional CMOS structures face limitations in scaling due to aggressive lithography requirements and limited access points for terminals, making it difficult to achieve high density and performance in integrated circuit devices.
Innovation Solution
The solution involves a three-dimensional stacked transistor structure where first and second field-effect transistors of one type are positioned at a first vertical level, and third and fourth field-effect transistors of another type are positioned at a second vertical level, with shared gate structures and a gate contact that are vertically aligned between the source and drain regions, allowing for increased cell height and improved wireability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional CMOS structures are used, then manufacturing process is simpler, but circuit wireability and access points for terminals are limited
Solution Approach 1:
The patent transitions from traditional planar CMOS structures to three-dimensional stacked transistor structures. Multiple transistor layers are vertically stacked with shared gate structures, increasing the number of access points for terminals from limited planar contacts to multiple vertical and lateral access points. This dimensional change enables improved circuit wireability without requiring aggressive lithography scaling.
2Quantity of substance
If device scaling is pursued to increase density, then more transistors fit in given area, but lithography requirements become more aggressive and difficult
Solution Approach 1:
Instead of continuing to scale transistor dimensions in the planar direction which demands aggressive lithography, the patent stacks multiple transistor layers vertically. This achieves higher transistor density by utilizing the third dimension (vertical stacking) rather than further reducing lateral dimensions, thereby avoiding the need for more aggressive lithography precision.
Solution Approach 2:
The patent combines multiple transistor structures into stacked configurations with shared gate structures. Multiple transistors share common gate electrodes and control structures, achieving high density through vertical integration and resource sharing rather than through continued lateral miniaturization requiring advanced lithography.
3Ease of operation
If more access points are added to improve wireability, then circuit performance improves, but structure becomes more complex
Solution Approach 1:
The stacked transistor structure provides multiple access points through vertical stacking, allowing terminals to be accessed from both lateral and vertical directions. This three-dimensional arrangement increases wireability options without proportionally increasing structural complexity, as the stacking methodology provides systematic access point multiplication.
Data Source
AI summary
A semiconductor structure includes a three-dimensional stacked transistor structure including first and second field-effect transistors of a first type at a first vertical level and third and fourth field-effect transistors of a second type at a second vertical level disposed over the first vertical level. The semiconductor structure also includes a first gate structure shared between the first and second field-effect transistors at the first vertical level, a second gate structure shared between the third and fourth field-effect transistors at the second vertical level, and a gate contact shared by the first and second gate structures. The wherein the first and second gate structures are vertically aligned with another in a layout of the three-dimensional stacked transistor structure between source drain/regions of the first, second, third and fourth field-effect transistors.