Stacked Transistor Vertical Interconnect for Lower Capacitance Routing
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Solution Overview
Problem
As semiconductor devices continue to increase in integration density and performance, challenges arise from fabrication and design, particularly in stacked device configurations like CFETs, where reducing feature sizes introduces additional complexities and limitations in interconnect routing and capacitance.
Innovation Solution
A vertical interconnect structure is introduced in stacked transistors, which extends through the gate stacks, reducing the aspect ratio of metal interconnects, and includes a dielectric layer to minimize capacitance and seam formation, allowing for improved process integration and increased routing flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If vertical interconnect structure is introduced extending through gate stacks, then routing flexibility is improved and capacitance is reduced, but device structure complexity increases
Solution Approach 1:
The patent transitions from planar interconnect routing to vertical interconnect routing by extending metal interconnect structures through the gate stacks in the vertical dimension. This allows signals to route underneath active devices rather than only along the surface, effectively adding a third dimension to the interconnect topology and enabling new routing paths that reduce capacitance and improve flexibility.
Solution Approach 2:
The vertical interconnect structure is nested within the existing transistor architecture by routing metal layers through the gate stack regions. The interconnect structure is embedded within the vertical space already defined by the gate stacks, allowing the interconnect to utilize the vertical volume without requiring additional lateral space or fundamentally altering the transistor active areas.
2Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated, but additional fabrication challenges and design complexities are introduced
Solution Approach 1:
By moving interconnect routing to the vertical dimension through gate stacks, the patent enables continued integration density improvements without proportionally increasing lateral interconnect complexity. The vertical routing path allows compact lateral footprints while maintaining signal integrity, effectively decoupling integration density from interconnect routing complexity.
3Reliability
If metal interconnect aspect ratio is reduced, then seam or void formation is avoided and manufacturing reliability improves, but interconnect structure complexity increases
Solution Approach 1:
The vertical interconnect structure is segmented into multiple metal layers with dielectric material positioned between them. This segmentation creates shorter individual metal segments with lower aspect ratios, avoiding the seam and void formation issues that would occur in a single continuous vertical metal structure, while still achieving the overall vertical routing function.
Solution Approach 2:
Dielectric material is introduced as an intermediary between metal interconnect layers in the vertical structure. This dielectric layer acts as a mediator that separates the metal segments, preventing direct metal-to-metal contact while maintaining the vertical routing function, and ensuring manufacturability by avoiding high aspect ratio metal structures.
Data Source
AI summary
In an embodiment, a semiconductor device may include a plurality of first nanostructures. The plurality of first nanostructures extend between first source/drain regions. The semiconductor device may also include a plurality of second nanostructures over the plurality of first nanostructures. The plurality of second nanostructures extend between second source/drain regions. The device may furthermore include a first gate stack around the plurality of first nanostructures. The device may in addition include a second gate stack over the first gate stack and disposed around the plurality of second nanostructures. The device may moreover include a vertical interconnect structure extending through the first and second gate stacks. The device may also include a frontside contact electrically coupled to a frontside of the vertical interconnect structure and a backside contact electrically coupled to a backside of the vertical interconnect structure.