3D Stacked Transistor Layout With Vertical Interconnect Customization
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to increase device density while maintaining efficiency and reducing complexity as devices scale down to sub-micron sizes, requiring innovative structures and methods to support complex functions in smaller form factors.
Innovation Solution
A 3D semiconductor apparatus is designed with repetitive initial structures that include stacked transistors and vertical conductive structures, where local interconnects and vertical connections are used to provide power and signal inputs, allowing for customization into different logic cells by adding or subtracting connections, thereby increasing density and simplifying the design process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D semiconductor device scaling is continued, then device density increases, but manufacturing complexity and difficulty increase significantly
Solution Approach 1:
The patent transitions from 2D planar device layout to 3D vertical stacking architecture. Multiple transistor layers are stacked vertically along the Z-direction, enabling device density multiplication without proportionally increasing manufacturing process complexity. The standardized layer repetition allows complex 3D structures to be built using extended 2D fabrication techniques.
Solution Approach 2:
The semiconductor device is segmented into multiple identical or similar transistor layers stacked vertically. Each layer contains source regions, drain regions, gate electrodes, and interlayer insulating films arranged in repeating patterns. This segmentation into modular units simplifies manufacturing by allowing replication of standardized layers.
2Area of moving object
If device dimensions are reduced to sub-micron sizes, then integration density increases, but processing and manufacturing complexity increases
Solution Approach 1:
The patent employs universal manufacturing processes that can handle both 2D and 3D structures. Standard semiconductor fabrication techniques such as chemical vapor deposition, sputtering, and etching are used to form vertical structures, gate electrodes, and interlayer insulating films in repetitive layers, making the manufacturing process scalable and adaptable.
Solution Approach 2:
Interlayer insulating films are formed preliminarily between transistor layers during the stacking process. These insulating films are prepared in advance as part of each layer's fabrication sequence, enabling subsequent layers to be built upon established structures without requiring complex post-assembly operations.
3Adaptability or versatility
If more complex functions are integrated, then device capability increases, but manufacturing complexity increases
Solution Approach 1:
The patent uses vertical stacking to integrate multiple transistor layers that can perform different logical functions. By arranging transistors in the vertical dimension rather than spreading them horizontally, the device achieves higher functional integration while maintaining manageable structural complexity through standardized layer repetition.
Solution Approach 2:
Multiple functional elements are merged into compact vertical stacks. Each stacked layer combines source regions, drain regions, gate electrodes, and interlayer insulating films into an integrated unit. This merging of functions in the vertical dimension reduces the overall device footprint while maintaining complex functionality.
Data Source
AI summary
A method for forming a semiconductor apparatus includes forming a plurality of repetitive initial structures over a substrate of the semiconductor apparatus. An initial structure in the plurality of repetitive initial structures is formed by forming a first stack of transistors along a Z direction substantially perpendicular to a substrate plane, and forming local interconnect structures. Each of the transistors in the first stack of transistors is sandwiched between two of the local interconnect structures. Vertical conductive structures are formed substantially parallel to the Z direction, a height of one of the vertical conductive structures along the Z direction being at least a height of the initial structure. The initial structure is functionalized into a final structure by forming one or more connections each electrically coupling one of the local interconnect structures to one of the vertical conductive structures.