Stacked Transistor Via Structure for Low-Resistance BSPDN Routing
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices requires improved integration and electrical characteristics, particularly in the development of semiconductor devices with fine patterns and Back Side Power Delivery Network (BSPDN) structures, where existing technologies face challenges in achieving optimal integration and electrical performance.
Innovation Solution
The semiconductor device incorporates insulating patterns, device isolation layers, gate structures, source/drain regions, via structures, and contact structures, with specific configurations such as varying via structure widths and barrier layers to enhance integration and electrical characteristics, including a via structure that reduces resistance by increasing and decreasing in width vertically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration is increased to achieve high performance and high speed, then productivity and functionality are improved, but manufacturing precision and electrical characteristics deteriorate due to fine pattern challenges
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional stacked transistors, stacking multiple transistor layers vertically to increase integration density while maintaining manufacturable pattern dimensions. This vertical stacking allows higher productivity without proportionally decreasing pattern fabrication precision.
Solution Approach 2:
Multiple transistor layers are nested vertically within a stacked configuration, with each layer containing source/drain regions, channel layers, and gate structures. This nesting approach increases the number of functional elements within a compact volume, improving integration while keeping individual pattern dimensions manageable.
2Productivity
If the degree of integration is increased with fine patterns, then productivity is improved, but electrical characteristics worsen due to increased resistance in confined structures
Solution Approach 1:
The via structure extends vertically through multiple transistor layers, utilizing the vertical dimension to create low-resistance electrical pathways that connect source/drain regions across stacked layers. This vertical via configuration reduces overall resistance compared to horizontal routing in confined planar structures.
Solution Approach 2:
The via structure employs varying width parameters along its vertical extent, with wider sections positioned to optimize electrical connection at critical interfaces between layers. This parameter variation reduces resistance by increasing conductive cross-sectional area where needed, while maintaining compact overall dimensions.
3Reliability
If via structure width is increased to reduce resistance, then electrical characteristics are improved, but device complexity increases
Solution Approach 1:
The via structure features localized width variations at specific vertical positions rather than uniform expansion throughout. Wider sections are strategically positioned at interfaces where low resistance is most critical, while other portions maintain narrower dimensions. This local quality approach reduces resistance where needed without proportionally increasing overall device complexity.
Solution Approach 2:
Instead of increasing via width uniformly in the horizontal plane (which would increase lateral complexity), the patent utilizes the vertical dimension to create width variations. The via structure's cross-sectional area changes along its vertical extent, allowing resistance optimization through vertical geometry control rather than horizontal expansion.
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A semiconductor device includes: insulating patterns; a device isolation layer on side surfaces of the insulating patterns; gate structures; source/drain regions (150) on the insulating patterns; a via structure (190) between the gate structures and between the source/drain regions; and contact structures (180) connected to the source/drain regions and the via structure, wherein the source/drain regions may include first source/drain regions (150A) and second source/drain regions (150B), wherein the via structure may extend from the same level as lower surfaces of the first source/drain regions to the same level as upper surfaces of the second source/drain regions, and the via structure may include a portion in which a width of the via structure increases and then decreases or decreases and then increases, wherein the contact structures may include a first contact structure contacting the first source/drain regions and a second contact structure contacting the second source/drain regions.