Stacked Transistor Contact Via Layout for Short-Free Scaling
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Solution Overview
Problem
As semiconductor structures and stacked transistor cells become increasingly smaller, the proximity of contact vias can lead to electrical shorts and failure points, compromising the scalability and functionality of the semiconductor structure.
Innovation Solution
Implementing vertically staggered and inverted contact vias in stacked transistors to maintain spacing and prevent shorts without increasing cell height or reducing contact via dimensions, achieved by varying the thickness and orientation of backside contacts and contact vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If contact vias are placed closer together to reduce device size, then device scaling is improved, but electrical shorts and failure points increase
Solution Approach 1:
The patent applies vertical staggering to contact vias, transitioning from a two-dimensional planar arrangement to a three-dimensional vertical arrangement. Contact vias are positioned at different vertical levels (first contact via at a first vertical level, second contact via at a second vertical level), which maintains adequate spacing while enabling closer lateral positioning. This dimensional change resolves the contradiction by allowing device scaling without compromising reliability.
Solution Approach 2:
The patent segments the contact via structure into multiple vertically separated components. Instead of a single planar layer of contact vias, the structure is divided into contact vias at different vertical levels, with intermediate structures (such as epitaxial regions and insulating layers) separating them. This segmentation allows closer overall device packaging while maintaining reliable electrical isolation between contacts.
2Volume of moving object
If contact via dimensions are reduced to enable smaller devices, then device scaling is improved, but manufacturing precision and reliability deteriorate
Solution Approach 1:
By moving the spacing requirement from the lateral dimension to the vertical dimension, the patent allows contact vias to maintain larger, more manufacturable dimensions in the lateral plane while achieving device scaling through vertical separation. The contact via dimensions can be optimized for manufacturing precision while the vertical staggering provides the size reduction.
3Reliability
If cell height is increased to space contact vias vertically, then electrical short prevention is improved, but device compactness deteriorates
Solution Approach 1:
The patent merges the contact via spacing function with other device structures. The vertical separation between contact vias is achieved through integration with epitaxial regions, insulating layers, and transistor structures that are already part of the device architecture. This merging allows vertical staggering for reliability without requiring additional height beyond what is already needed for device operation.
Solution Approach 2:
The patent utilizes the vertical dimension for contact via separation while maintaining compact lateral dimensions. By arranging contact vias at different vertical levels rather than spreading them laterally, the design achieves reliable electrical isolation without increasing the overall device footprint, thus maintaining compactness while improving reliability.
Data Source
AI summary
The present disclosure provides a semiconductor structure, a system, and a method of forming a stacked transistor structure with vertically staggered contact vias. The semiconductor structure may include a first stacked transistor cell including a first backside contact having a first contact thickness. The semiconductor structure may also include a second stacked transistor cell including a second backside contact having a second contact thickness different from the first contact thickness. The system may include a semiconductor structure. The method may include forming a first bottom epi and a second bottom epi, filling a first opening in the first stacked transistor cell with one or more metal materials, recessing the one or more metal materials, and filling a second opening in the second stacked transistor cell with the one or more metal materials.