Stacked Transistor Vt Tuning Using Patterned Dipole Layers
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Solution Overview
Problem
Existing threshold voltage tuning techniques for multigate devices, such as fin-like field effect transistors and gate-all-around transistors, are inadequate for achieving multiple threshold voltages due to limited space for tuning and the need to minimize the use of different work function metals.
Innovation Solution
A dipole engineering technique involving patterned dipole dopant source layers and a thermal drive-in process is used to tune the threshold voltages of transistors without adding additional layers, allowing for multiple threshold voltages to be achieved by configuring the thickness and material characteristics of the dipole dopant source layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional work function metal tuning is used for multigate devices, then threshold voltage can be adjusted, but device area is insufficient and multiple metal types are required
Solution Approach 1:
The patent changes the approach from using different work function metals to using dipole dopants with varying dipole moments. By adjusting the type and concentration of dipole dopants (e.g., different metal atoms or molecular dipoles), the threshold voltage can be precisely tuned without being constrained by device area or requiring multiple metal layers. This parameter change enables continuous threshold voltage adjustment within a single device structure.
2Adaptability or versatility
If multiple work function metals are used to achieve multiple threshold voltages, then transistor performance can be optimized, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent implements a universal dipole dopant approach where a single gate electrode structure serves multiple functions by incorporating different dipole dopants. The same gate electrode can be tuned to provide different threshold voltages for n-type and p-type transistors, or for different performance modes, eliminating the need for separate work function metal layers for each transistor type. This multi-functionality reduces device complexity while maintaining the capability for multiple threshold voltages.
3Productivity
If device stacking is implemented for further scaling, then integration density improves, but threshold voltage tuning becomes more challenging
Solution Approach 1:
The patent transitions from planar threshold voltage tuning to vertical dipole dopant insertion. By introducing dipole dopants through the gate dielectric layer in the vertical dimension, the method enables precise threshold voltage control in stacked device architectures where horizontal tuning space is limited. This dimensional change allows independent tuning of each transistor in the stack without increasing lateral footprint, thereby maintaining integration density while restoring tuning precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables flexible and volumeless threshold voltage tuning, allowing for transistors to have multiple threshold voltages, enhancing performance and reducing power consumption without the need for additional materials, suitable for nano-sized transistors like FinFETs and GAA transistors.
Implementation Method 1
A dipole engineering technique involving patterned dipole dopant source layers and a thermal drive-in process is used to tune the threshold voltages of transistors
Data Source
AI summary
Dipole engineering techniques for stacked device structures are disclosed herein. According to various aspects of the present disclosure, an exemplary dipole engineering technique includes (1) forming at least two patterned dipole dopant source layers having different patterns and covering gate dielectric layers of some transistors, but not other transistors, (2) performing a thermal drive-in process (e.g., a dipole drive-in anneal), and (3) after removing the dipole dopant source layer, forming gate electrodes for the transistors, where a same gate electrode material is used for the transistors. Thickness(es) and/or material characteristics (e.g., dipole dopant) of the patterned dipole dopant source layers and/or parameters of the thermal drive-in process may be configured to achieve desired threshold voltages. Such technique may provide 2N threshold voltages (Vt), where N is a number of patterned dipole dopant source layers formed on the gate dielectric layers of the transistors to tune their threshold voltages.