Stacked Multi-Gate Transistor Wall Structure for Channel Uniformity
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Solution Overview
Problem
Existing semiconductor devices face challenges in scaling integration density and maintaining consistent performance across stacked multi-gate transistors due to variations in channel width and thickness, leading to differences in transistor characteristics.
Innovation Solution
A semiconductor device design featuring a substrate with a wall structure that isolates and intersects multiple active patterns, where the width of the wall structure increases away from the substrate, and the thickness and number of bridge patterns are controlled to maintain consistent channel area sizes across stacked transistors, minimizing characteristic differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-gate transistor uses a three-dimensional channel structure, then scaling integration density is improved and current control capability is enhanced, but variations in channel width and thickness lead to inconsistent transistor characteristics across stacked devices
Solution Approach 1:
The wall structure is designed with an asymmetric tapered shape where the width in the second direction increases as the wall structure extends away from the substrate. This asymmetric geometry compensates for the natural tapering of the three-dimensional channel, ensuring that the channel width remains uniform across different stacked levels despite the vertical stacking configuration.
Solution Approach 2:
The patent adjusts the wall structure width parameter dynamically - specifically, the width in the second direction varies along the first direction (increasing away from the substrate). This parameter change in the wall structure compensates for variations in channel dimensions, maintaining consistent channel width and thickness across stacked transistors.
2Manufacturing precision
If the wall structure width is increased away from the substrate, then channel area uniformity is improved, but device structural complexity increases
Solution Approach 1:
The wall structure employs an asymmetric tapered geometry rather than a symmetric uniform width. This asymmetric design, while structurally more complex, achieves the goal of maintaining uniform channel area across stacked transistors by compensating for vertical dimension variations through controlled width variation.
Data Source
AI summary
A semiconductor device includes, a substrate, a wall structure disposed on the substrate and extending in a first direction, wherein the wall structure includes a first side surface and a second side surface opposite to the first side surface in a second direction intersecting the first direction, a first lower active pattern disposed on the first side surface and including at least one first lower bridge pattern spaced apart from the substrate, a first upper active pattern disposed on the first side surface and including at least one first upper bridge pattern spaced further apart from the substrate than the first lower active pattern, a first gate structure disposed on the first side surface and intersecting the first lower active pattern and the first upper active pattern, a second lower active pattern disposed on the second side surface and including at least one second lower bridge pattern spaced apart from the substrate, a second upper active pattern disposed on the second side surface and including at least one second upper bridge pattern spaced apart from the substrate than the second lower active pattern, and a second gate structure disposed on the second side surface and intersecting the second lower active pattern and the second upper active pattern, wherein a width in the second direction of the wall structure increases as the wall structure extends away from the substrate.