Stacked Transistors with Common Gate for Lower Parasitic Capacitance
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Solution Overview
Problem
Three-dimensional transistor structures face challenges such as parasitic capacitance and complex deposition and removal of gate metal, with undefined borders complicating the formation of inner spacers.
Innovation Solution
A sacrificial layer is used to define borders between upper and lower transistors, which is then replaced with an isolation layer to form a common gate, improving control over inner spacer formation and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional transistor structures are used to increase transistor density, then transistor density is improved, but parasitic capacitance increases
Solution Approach 1:
An isolation region filled with dielectric material is introduced as an intermediary element between the upper and lower transistors. This dielectric insertion acts as a mediator that electrically isolates the gate electrodes of stacked transistors, reducing parasitic capacitance while allowing the three-dimensional structure to maintain high transistor density.
2Manufacturing precision
If inner spacers are formed for three-dimensional transistor structures, then manufacturing precision is improved, but the process becomes complicated and difficult to control
Solution Approach 1:
A sacrificial layer is deposited in advance between the upper and lower transistors before forming the isolation region. This preliminary sacrificial layer serves as a template and boundary definition, simplifying the subsequent formation of inner spacers and isolation structures by providing pre-defined geometric constraints and etch stop layers.
Solution Approach 2:
The sacrificial layer is used as a temporary, disposable element that is deposited, utilized for defining borders and guiding spacer formation, and then removed. This disposable sacrificial layer simplifies the overall process by providing easy-to-deposit material that can be selectively removed to create the desired isolation region geometry.
3Reliability
If gate metal is deposited and removed for three-dimensional transistor structures, then device performance is improved, but the process becomes complicated and difficult to control
Solution Approach 1:
The isolation region filled with dielectric material serves as an intermediary barrier that simplifies gate metal deposition and removal processes. By providing a pre-defined isolated region, the gate metal can be deposited and patterned more easily without interfering with adjacent structures, improving process controllability while maintaining device performance.
Data Source
AI summary
Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.