Stacked Transistors Sharing Common Gate for Dynamic Logic Area Reduction
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Solution Overview
Problem
Dynamic logic circuits in integrated circuits face challenges in area efficiency due to the need for separate transistors for precharge and evaluate phases, leading to increased die size and complexity.
Innovation Solution
Implementing a monolithic three-dimensional integrated circuit structure with transistors from different device strata sharing a common gate electrode, allowing for area savings by compressing P-type precharge transistors over N-type evaluate transistors and enabling the use of shared gate electrodes in inverters, NAND, and NOR gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate transistors are used for precharge and evaluate phases in dynamic logic circuits, then the circuit functionality is maintained, but the die area increases and complexity increases
Solution Approach 1:
The patent merges the precharge transistor and evaluate transistor into a single stacked transistor structure where the P-type precharge transistor is positioned directly over the N-type evaluate transistor. Both transistors share a common gate electrode and control signal, allowing them to perform both precharge and evaluate functions sequentially without requiring separate transistor instances, thereby reducing die area while maintaining circuit functionality.
Solution Approach 2:
The stacked transistor structure serves multiple functions: the same physical structure performs both precharge operation (when clock is low) and evaluate operation (when clock is high). This multi-functional design eliminates the need for separate dedicated transistors for each phase, reducing overall circuit complexity and area occupation.
2Reliability
If separate transistors are used for precharge and evaluate phases in dynamic logic circuits, then the circuit functionality is maintained, but the device complexity increases
Solution Approach 1:
The patent merges the precharge transistor and evaluate transistor into a single stacked transistor structure where the P-type precharge transistor is positioned directly over the N-type evaluate transistor. Both transistors share a common gate electrode and control signal, allowing them to perform both precharge and evaluate functions sequentially without requiring separate transistor instances, thereby reducing die area while maintaining circuit functionality.
Solution Approach 2:
The stacked transistor structure serves multiple functions: the same physical structure performs both precharge operation (when clock is low) and evaluate operation (when clock is high). This multi-functional design eliminates the need for separate dedicated transistors for each phase, reducing overall circuit complexity and area occupation.
3Area of stationary object
If transistors are stacked and share a common gate electrode, then die area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements a nested structure where the N-type evaluate transistor is positioned directly beneath the P-type precharge transistor in vertical stacking. This nested arrangement allows both transistors to share the same footprint area and common gate electrode, maximizing space utilization while the fabrication process ensures proper alignment through standardized manufacturing techniques.
Data Source
AI summary
A dynamic logic circuit including a first transistor within a first device stratum of a substrate; and a second transistor within a second device stratum of the substrate that is different from the first device stratum, wherein the first transistor and the second transistor share a common gate electrode. A method including disposing a second semiconductor body of a second transistor on a first semiconductor body of a first transistor in a first device stratum on a substrate, the second semiconductor body defining a second device stratum; and forming a common gate electrode on each of the semiconductor body and the second semiconductor body.