Vertically Stacked Transistors With Shared Gate for Diffusion Control
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Solution Overview
Problem
As semiconductor devices are scaled down to increase device density, the lateral spacing between adjacent transistors becomes increasingly difficult to manage without negatively affecting device performance, leading to issues such as diffusion of elements between semiconductor layers and reduced reliability and yield.
Innovation Solution
The transistors are vertically stacked with a shared gate electrode, where the n-channel transistor is stacked over the p-channel transistor, maintaining a large lateral offset to prevent diffusion and using different dielectric materials to optimize performance, thereby reducing the lateral footprint and enhancing device density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If lateral spacing between adjacent transistors is reduced to increase device density, then device density increases, but element diffusion between semiconductor layers occurs and reliability deteriorates
Solution Approach 1:
The patent transitions from lateral arrangement to vertical stacking of transistors, moving the density improvement strategy from the horizontal plane to the vertical dimension. Multiple transistors are stacked above each other along the vertical axis, allowing higher device density without reducing lateral spacing between adjacent devices on the same layer.
Solution Approach 2:
The patent divides the transistor structure into multiple vertically separated layers with insulating layers between them. This segmentation prevents direct interaction and element diffusion between adjacent transistors while maintaining electrical functionality, thus improving reliability alongside density.
2Productivity
If lateral spacing between adjacent transistors is reduced to increase device density, then device density increases, but manufacturing precision requirements increase due to diffusion prevention needs
Solution Approach 1:
By stacking transistors vertically rather than arranging them laterally, the patent eliminates the need for precise lateral spacing control. The vertical separation between layers provides natural isolation, reducing manufacturing precision requirements for spacing while still achieving high device density.
Solution Approach 2:
Insulating layers are introduced as intermediary structures between vertically stacked transistors. These intermediary layers provide physical and electrical isolation, preventing element diffusion without requiring extremely precise lateral spacing, thus lowering manufacturing precision requirements.
3Reliability
If different dielectric materials are used to optimize transistor performance, then transistor performance improves, but device complexity increases
Solution Approach 1:
Different dielectric materials are selectively applied to specific transistor types (n-channel vs. p-channel) based on their specific performance requirements. This local optimization allows each transistor type to use the most suitable dielectric material, improving overall transistor performance while managing complexity through targeted rather than universal material selection.
Data Source
AI summary
Various embodiments of the present application are directed towards an integrated chip (IC) including a lower dielectric structure over a semiconductor substrate. A gate structure is over the lower dielectric structure. The gate structure comprises a first surface opposite a second surface. A first semiconductor layer is arranged between the first surface of the gate structure and the lower dielectric structure. A second semiconductor layer is over the second surface of the gate structure.